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git://nv-tegra.nvidia.com/linux-nvgpu.git
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gpu: nvgpu: Dynamic betacb size
Allow querying and setting default betacb size via debugfs. For global buffers the value takes effect upon first boot of GPU, and has no effect after that. Bug 1628352 Change-Id: Ib63f4299249c41eab1b36cc501b525cc54211195 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/733328
This commit is contained in:
committed by
Ishan Mittal
parent
96ffe0c64d
commit
d20afe7bd4
@@ -1518,6 +1518,7 @@ static int gk20a_probe(struct platform_device *dev)
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S_IRUGO|S_IWUSR,
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platform->debugfs,
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&gk20a->mm.disable_bigpage);
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gr_gk20a_debugfs_init(gk20a);
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gk20a_pmu_debugfs_init(dev);
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gk20a_cde_debugfs_init(dev);
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#endif
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@@ -472,6 +472,7 @@ struct gk20a {
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struct dentry *debugfs_gr_idle_timeout_default;
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struct dentry *debugfs_bypass_smmu;
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struct dentry *debugfs_disable_bigpage;
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struct dentry *debugfs_gr_default_attrib_cb_size;
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#endif
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struct gk20a_ctxsw_ucode_info ctxsw_ucode_info;
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@@ -21,6 +21,7 @@
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#include <linux/mm.h> /* for totalram_pages */
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#include <linux/scatterlist.h>
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#include <linux/tegra-soc.h>
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#include <linux/debugfs.h>
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#include <uapi/linux/nvgpu.h>
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#include <linux/vmalloc.h>
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#include <linux/dma-mapping.h>
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@@ -54,6 +55,7 @@
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#include "dbg_gpu_gk20a.h"
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#include "debug_gk20a.h"
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#include "semaphore_gk20a.h"
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#include "platform_gk20a.h"
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#define BLK_SIZE (256)
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@@ -6909,8 +6911,9 @@ static void gr_gk20a_cb_size_default(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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gr->attrib_cb_default_size =
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gr_gpc0_ppc0_cbm_cfg_size_default_v();
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if (!gr->attrib_cb_default_size)
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gr->attrib_cb_default_size =
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gr_gpc0_ppc0_cbm_cfg_size_default_v();
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gr->alpha_cb_default_size =
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gr_gpc0_ppc0_cbm_cfg2_size_default_v();
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}
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@@ -7267,6 +7270,18 @@ static int gr_gk20a_dump_gr_status_regs(struct gk20a *g,
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return 0;
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}
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int gr_gk20a_debugfs_init(struct gk20a *g)
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{
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struct gk20a_platform *platform = platform_get_drvdata(g->dev);
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g->debugfs_gr_default_attrib_cb_size =
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debugfs_create_u32("gr_default_attrib_cb_size",
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S_IRUGO|S_IWUSR, platform->debugfs,
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&g->gr.attrib_cb_default_size);
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return 0;
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}
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void gk20a_init_gr_ops(struct gpu_ops *gops)
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{
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gops->gr.access_smpc_reg = gr_gk20a_access_smpc_reg;
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@@ -495,5 +495,6 @@ int gr_gk20a_alloc_gr_ctx(struct gk20a *g,
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void gr_gk20a_free_gr_ctx(struct gk20a *g,
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struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx);
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int gr_gk20a_halt_pipe(struct gk20a *g);
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int gr_gk20a_debugfs_init(struct gk20a *g);
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#endif /*__GR_GK20A_H__*/
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@@ -85,8 +85,9 @@ static void gr_gm20b_cb_size_default(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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gr->attrib_cb_default_size =
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gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
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if (!gr->attrib_cb_default_size)
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gr->attrib_cb_default_size =
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gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
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gr->alpha_cb_default_size =
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gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
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}
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