gpu: nvgpu: detect vidmem configuration from HW

Read video memory size from hardware during initialization for devices
that support it.

JIRA DNVGPU-14

Change-Id: If190f2d89f7148520ee274ca674f972987c8056d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1157215
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Konsta Holtta
2016-05-20 09:12:23 +03:00
committed by Terje Bergstrom
parent 2219f38727
commit d215bc1107
9 changed files with 149 additions and 1 deletions

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@@ -80,6 +80,7 @@ nvgpu-y := \
gm206/hal_gm206.o \ gm206/hal_gm206.o \
gm206/gr_gm206.o \ gm206/gr_gm206.o \
gm206/acr_gm206.o \ gm206/acr_gm206.o \
gm206/mm_gm206.o \
gm206/pmu_gm206.o \ gm206/pmu_gm206.o \
gm206/ce_gm206.o gm206/ce_gm206.o

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@@ -524,6 +524,7 @@ struct gpu_ops {
u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl,
u32 flags); u32 flags);
int (*bar1_bind)(struct gk20a *g, u64 bar1_iova); int (*bar1_bind)(struct gk20a *g, u64 bar1_iova);
size_t (*get_vidmem_size)(struct gk20a *g);
} mm; } mm;
struct { struct {
int (*init_therm_setup_hw)(struct gk20a *g); int (*init_therm_setup_hw)(struct gk20a *g);

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@@ -613,6 +613,20 @@ static void gk20a_init_pramin(struct mm_gk20a *mm)
mm->force_pramin = GK20A_FORCE_PRAMIN_DEFAULT; mm->force_pramin = GK20A_FORCE_PRAMIN_DEFAULT;
} }
static int gk20a_init_vidmem(struct mm_gk20a *mm)
{
struct gk20a *g = mm->g;
size_t size = g->ops.mm.get_vidmem_size ?
g->ops.mm.get_vidmem_size(g) : 0;
if (!size)
return 0;
mm->vidmem_size = size;
return 0;
}
int gk20a_init_mm_setup_sw(struct gk20a *g) int gk20a_init_mm_setup_sw(struct gk20a *g)
{ {
struct mm_gk20a *mm = &g->mm; struct mm_gk20a *mm = &g->mm;
@@ -637,6 +651,7 @@ int gk20a_init_mm_setup_sw(struct gk20a *g)
(int)(mm->channel.kernel_size >> 20)); (int)(mm->channel.kernel_size >> 20));
gk20a_init_pramin(mm); gk20a_init_pramin(mm);
gk20a_init_vidmem(mm);
err = gk20a_alloc_sysmem_flush(g); err = gk20a_alloc_sysmem_flush(g);
if (err) if (err)

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@@ -372,6 +372,8 @@ struct mm_gk20a {
#else #else
bool force_pramin; /* via debugfs */ bool force_pramin; /* via debugfs */
#endif #endif
size_t vidmem_size;
}; };
int gk20a_mm_init(struct mm_gk20a *mm); int gk20a_mm_init(struct mm_gk20a *mm);

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@@ -21,6 +21,7 @@
#include "gm20b/mc_gm20b.h" #include "gm20b/mc_gm20b.h"
#include "gm20b/ltc_gm20b.h" #include "gm20b/ltc_gm20b.h"
#include "gm20b/mm_gm20b.h" #include "gm20b/mm_gm20b.h"
#include "gm206/mm_gm206.h"
#include "ce_gm206.h" #include "ce_gm206.h"
#include "gm20b/fb_gm20b.h" #include "gm20b/fb_gm20b.h"
#include "gm20b/pmu_gm20b.h" #include "gm20b/pmu_gm20b.h"
@@ -188,7 +189,7 @@ int gm206_init_hal(struct gk20a *g)
gm206_init_fifo(gops); gm206_init_fifo(gops);
gm206_init_ce(gops); gm206_init_ce(gops);
gm20b_init_gr_ctx(gops); gm20b_init_gr_ctx(gops);
gm20b_init_mm(gops); gm206_init_mm(gops);
gm206_init_pmu_ops(gops); gm206_init_pmu_ops(gops);
gm20b_init_clk_ops(gops); gm20b_init_clk_ops(gops);
gm20b_init_regops(gops); gm20b_init_regops(gops);

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@@ -0,0 +1,61 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_fbpa_gp106_h_
#define _hw_fbpa_gp106_h_
static inline u32 fbpa_cstatus_r(void)
{
return 0x0010f20c;
}
static inline u32 fbpa_cstatus_ramamount_v(u32 r)
{
return (r >> 0) & 0x1ffff;
}
#endif

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@@ -74,6 +74,14 @@ static inline u32 top_num_fbps_value_v(u32 r)
{ {
return (r >> 0) & 0x1f; return (r >> 0) & 0x1f;
} }
static inline u32 top_num_fbpas_r(void)
{
return 0x0002243c;
}
static inline u32 top_num_fbpas_value_v(u32 r)
{
return (r >> 0) & 0x1f;
}
static inline u32 top_ltc_per_fbp_r(void) static inline u32 top_ltc_per_fbp_r(void)
{ {
return 0x00022450; return 0x00022450;

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@@ -0,0 +1,35 @@
/*
* GM206 memory management
*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "gk20a/gk20a.h"
#include "gm20b/mm_gm20b.h"
#include "hw_fbpa_gm206.h"
#include "hw_top_gm206.h"
static size_t gm206_mm_get_vidmem_size(struct gk20a *g)
{
u32 fbpas = top_num_fbpas_value_v(
gk20a_readl(g, top_num_fbpas_r()));
u32 ram = fbpa_cstatus_ramamount_v(
gk20a_readl(g, fbpa_cstatus_r()));
return (size_t)fbpas * ram * SZ_1M;
}
void gm206_init_mm(struct gpu_ops *gops)
{
gm20b_init_mm(gops);
gops->mm.get_vidmem_size = gm206_mm_get_vidmem_size;
}

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@@ -0,0 +1,24 @@
/*
* GM206 memory management
*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef MM_GM206_H
#define MM_GM206_H
struct gpu_ops;
void gm206_init_mm(struct gpu_ops *gops);
#endif