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gpu: nvgpu: update SSMD array size

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-Update SSMD array size to hold all supported super-surface
members
-Handle the error and report if invalid SSMD ID is found.

issue: At present SSMD array size set to 32 but overall
33 super-surface members are supported, when 33rd member
accessed system crash happened due to overflow access,
so fixing it by setting the SSMD array size to actual
number of super-surface members supported

Bug 200721968
Bug 200721966

Change-Id: I5ba1084a661d7497056f13a053d2fc79d50f595c
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2528569
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
mkumbar
2021-05-12 20:50:29 +05:30
committed by mobile promotions
parent 2514814851
commit d2349b32ec
4 changed files with 29 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/pmu/ipc/pmu_msg.c
View File

@@ -475,8 +475,11 @@ static int pmu_process_init_msg(struct nvgpu_pmu *pmu,
nvgpu_pmu_allocator_dmem_init(g, pmu, &pmu->dmem, init);
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_PMU_SUPER_SURFACE)) {
nvgpu_pmu_ss_create_ssmd_lookup_table(g,
err = nvgpu_pmu_ss_create_ssmd_lookup_table(g,
pmu, pmu->super_surface);
if (err != 0) {
goto exit;
}
}
nvgpu_pmu_set_fw_ready(g, pmu, true);

22
drivers/gpu/nvgpu/common/pmu/super_surface/super_surface.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -76,18 +76,20 @@ struct nvgpu_mem *nvgpu_pmu_super_surface_mem(struct gk20a *g,
* table, i.e one table is for SET ID TYPE & second table for
* GET_STATUS ID_TYPE.
*/
void nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g,
int nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss)
{
struct super_surface_member_descriptor ssmd;
u32 ssmd_size = (u32)
sizeof(struct super_surface_member_descriptor);
u32 idx = 0U;
int err = 0;
nvgpu_log_fn(g, " ");
if (ss == NULL) {
return;
nvgpu_err(g, "SS not allocated");
return -ENOMEM;
}
for (idx = 0U; idx < NV_PMU_SUPER_SURFACE_MEMBER_DESCRIPTOR_COUNT;
@@ -109,6 +111,12 @@ void nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g,
* during member info fetch.
*/
ssmd.id &= 0xFFFFU;
if (ssmd.id >= NV_PMU_SUPER_SURFACE_MEMBER_COUNT) {
nvgpu_err(g, "incorrect ssmd id %d", ssmd.id);
nvgpu_err(g, "Failed to create SSMD table");
err = -EINVAL;
break;
}
/*use member ID as index for lookup table too*/
(void) memcpy(&ss->ssmd_set[ssmd.id], &ssmd,
ssmd_size);
@@ -121,6 +129,12 @@ void nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g,
* during member info fetch.
*/
ssmd.id &= 0xFFFFU;
if (ssmd.id >= NV_PMU_SUPER_SURFACE_MEMBER_COUNT) {
nvgpu_err(g, "incorrect ssmd id %d", ssmd.id);
nvgpu_err(g, "failed to create SSMD table");
err = -EINVAL;
break;
}
/*use member ID as index for lookup table too*/
(void) memcpy(&ss->ssmd_get_status[ssmd.id], &ssmd,
ssmd_size);
@@ -128,6 +142,8 @@ void nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g,
continue;
}
}
return err;
}
u32 nvgpu_pmu_get_ss_member_set_offset(struct gk20a *g,

7
drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,7 @@
#include <nvgpu/pmu/pmuif/cmn.h>
#include <nvgpu/flcnif_cmn.h>
#include <common/pmu/boardobj/ucode_boardobj_inf.h>
#include <nvgpu/pmu/super_surface.h>
struct nvgpu_mem;
@@ -103,10 +104,10 @@ struct nvgpu_pmu_super_surface {
struct nvgpu_mem super_surface_buf;
struct super_surface_member_descriptor
ssmd_set[NV_PMU_SUPER_SURFACE_MEMBER_DESCRIPTOR_COUNT];
ssmd_set[NV_PMU_SUPER_SURFACE_MEMBER_COUNT];
struct super_surface_member_descriptor
ssmd_get_status[NV_PMU_SUPER_SURFACE_MEMBER_DESCRIPTOR_COUNT];
ssmd_get_status[NV_PMU_SUPER_SURFACE_MEMBER_COUNT];
};
#endif /* SUPER_SURFACE_PRIV_H */

4
drivers/gpu/nvgpu/include/nvgpu/pmu/super_surface.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -63,7 +63,7 @@ u32 nvgpu_pmu_get_ss_member_get_status_offset(struct gk20a *g,
struct nvgpu_pmu *pmu, u32 member_id);
u32 nvgpu_pmu_get_ss_member_get_status_size(struct gk20a *g,
struct nvgpu_pmu *pmu, u32 member_id);
void nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g,
int nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss);
struct nvgpu_mem *nvgpu_pmu_super_surface_mem(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss);