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gpu: nvgpu: smid programming

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Populate chip specific sm id table.

JIRA GV11B-21

Change-Id: I58869b2c3e55449a7d999ddf73d6eb7b359b2a07
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1227095
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2016-09-26 08:50:23 -07:00
committed by mobile promotions
parent 2c59031a19
commit d37a573c45
4 changed files with 16 additions and 5 deletions
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1
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -302,6 +302,7 @@ struct gpu_ops {
u32 graphics_preempt_mode,
u32 compute_preempt_mode);
int (*fuse_override)(struct gk20a *g);
void (*init_sm_id_table)(struct gk20a *g);
int (*load_smid_config)(struct gk20a *g);
void (*program_sm_id_numbering)(struct gk20a *g,
u32 gpc, u32 tpc, u32 smid);

11
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -1293,7 +1293,7 @@ static void gr_gk20a_program_active_tpc_counts(struct gk20a *g, u32 gpc_index)
gr_gpc0_gpm_sd_active_tpcs_num_f(gr->gpc_tpc_count[gpc_index]));
}
static void gr_gk20a_init_sm_id_table(struct gk20a *g)
void gr_gk20a_init_sm_id_table(struct gk20a *g)
{
u32 gpc, tpc;
u32 sm_id = 0;
@@ -1304,6 +1304,9 @@ static void gr_gk20a_init_sm_id_table(struct gk20a *g)
if (tpc < g->gr.gpc_tpc_count[gpc]) {
g->gr.sm_to_cluster[sm_id].tpc_index = tpc;
g->gr.sm_to_cluster[sm_id].gpc_index = gpc;
g->gr.sm_to_cluster[sm_id].sm_index = 0;
g->gr.sm_to_cluster[sm_id].global_tpc_index =
sm_id;
sm_id++;
}
}
@@ -1339,9 +1342,10 @@ int gr_gk20a_init_fs_state(struct gk20a *g)
gk20a_dbg_fn("");
gr_gk20a_init_sm_id_table(g);
if (g->ops.gr.init_sm_id_table)
g->ops.gr.init_sm_id_table(g);
for (sm_id = 0; sm_id < gr->tpc_count; sm_id++) {
for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) {
tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index;
gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index;
@@ -9112,6 +9116,7 @@ void gk20a_init_gr_ops(struct gpu_ops *gops)
gops->gr.get_preemption_mode_flags = gr_gk20a_get_preemption_mode_flags;
gops->gr.program_active_tpc_counts = gr_gk20a_program_active_tpc_counts;
gops->gr.program_sm_id_numbering = gr_gk20a_program_sm_id_numbering;
gops->gr.init_sm_id_table = gr_gk20a_init_sm_id_table;
gops->gr.is_ltcs_ltss_addr = gr_gk20a_is_ltcs_ltss_addr_stub;
gops->gr.is_ltcn_ltss_addr = gr_gk20a_is_ltcn_ltss_addr_stub;
gops->gr.split_lts_broadcast_addr =

8
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
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@@ -174,8 +174,10 @@ struct zbc_query_params {
};
struct sm_info {
u8 gpc_index;
u8 tpc_index;
u32 gpc_index;
u32 tpc_index;
u32 sm_index;
u32 global_tpc_index;
};
#if defined(CONFIG_GK20A_CYCLE_STATS)
@@ -662,6 +664,8 @@ void gk20a_gr_enable_gpc_exceptions(struct gk20a *g);
int gr_gk20a_commit_global_timeslice(struct gk20a *g,
struct channel_gk20a *c, bool patch);
void gr_gk20a_init_sm_id_table(struct gk20a *g);
static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode)
{
switch (graphics_preempt_mode) {

1
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
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@@ -1561,6 +1561,7 @@ void gm20b_init_gr(struct gpu_ops *gops)
gops->gr.suspend_contexts = gr_gk20a_suspend_contexts;
gops->gr.get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags;
gops->gr.fuse_override = gm20b_gr_fuse_override;
gops->gr.init_sm_id_table = gr_gk20a_init_sm_id_table;
gops->gr.load_smid_config = gr_gm20b_load_smid_config;
gops->gr.program_sm_id_numbering = gr_gm20b_program_sm_id_numbering;
gops->gr.is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr;