nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: fix MISRA 8.6 errors hal.fifo.pbdma

Browse Source 
Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions. This patch fixes 8.6 issues in nvgpu/hal/fifo/
pbdma_gm20b.h

Jira NVGPU-3822

Change-Id: I601c5ba65fe282a04d1c85a5e20318a1d9d9a44f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2154400
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-07-16 16:00:23 -07:00
committed by mobile promotions
parent 6f21c665ce
commit d3fef630f5
1 changed files with 18 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h
View File

@@ -30,15 +30,11 @@ struct nvgpu_debug_context;
struct nvgpu_channel_dump_info;
struct nvgpu_gpfifo_entry;
void gm20b_pbdma_intr_enable(struct gk20a *g, bool enable);
bool gm20b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id,
u32 pbdma_intr_0, u32 *error_notifier);
bool gm20b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id,
u32 pbdma_intr_1, u32 *error_notifier);
bool gm20b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id,
u32 *error_notifier);
u32 gm20b_pbdma_get_signature(struct gk20a *g);
u32 gm20b_pbdma_read_data(struct gk20a *g, u32 pbdma_id);
void gm20b_pbdma_reset_header(struct gk20a *g, u32 pbdma_id);
void gm20b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
@@ -51,20 +47,14 @@ void gm20b_pbdma_format_gpfifo_entry(struct gk20a *g,
u64 pb_gpu_va, u32 method_size);
u32 gm20b_pbdma_device_fatal_0_intr_descs(void);
u32 gm20b_pbdma_channel_fatal_0_intr_descs(void);
u32 gm20b_pbdma_restartable_0_intr_descs(void);
void gm20b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id);
void gm20b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info);
void gm20b_pbdma_setup_hw(struct gk20a *g);
u32 gm20b_pbdma_get_gp_base(u64 gpfifo_base);
u32 gm20b_pbdma_get_gp_base_hi(u64 gpfifo_base, u32 gpfifo_entry);
u32 gm20b_pbdma_get_fc_formats(void);
u32 gm20b_pbdma_get_fc_pb_header(void);
u32 gm20b_pbdma_get_fc_subdevice(void);
u32 gm20b_pbdma_get_fc_target(void);
u32 gm20b_pbdma_get_ctrl_hce_priv_mode_yes(void);
@@ -72,4 +62,20 @@ u32 gm20b_pbdma_get_userd_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem);
u32 gm20b_pbdma_get_userd_addr(u32 addr_lo);
u32 gm20b_pbdma_get_userd_hi_addr(u32 addr_hi);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gm20b_pbdma_intr_enable(struct gk20a *g, bool enable);
bool gm20b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id,
u32 pbdma_intr_1, u32 *error_notifier);
u32 gm20b_pbdma_get_signature(struct gk20a *g);
u32 gm20b_pbdma_channel_fatal_0_intr_descs(void);
void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info);
void gm20b_pbdma_setup_hw(struct gk20a *g);
u32 gm20b_pbdma_get_fc_formats(void);
u32 gm20b_pbdma_get_fc_pb_header(void);
#endif
#endif /* NVGPU_PBDMA_GM20B_H */