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gpu: nvgpu: add vmid param to fecs trace bind_channel

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OS specific implementation of fecs trace bind_channel function
needs to handle special case for vserver to retrieve vmid from
channel id. Native code should be independent of server code.
Modify struct fecs_trace member function bind_channel to pass
vmid parameter enabling retrieving and passing vmid from server
code.

Jira GVSCI-44

Change-Id: I96223376f2068e2cbf60a9c9b35ff564a65e5dc3
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970693
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Aparna Das
2018-12-10 18:27:53 -08:00
committed by mobile promotions
parent 906643f184
commit d4f1a138dc
4 changed files with 8 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -436,7 +436,7 @@ clean:
}
int gk20a_fecs_trace_bind_channel(struct gk20a *g,
struct channel_gk20a *ch, struct nvgpu_gr_ctx *gr_ctx)
struct channel_gk20a *ch, u32 vmid, struct nvgpu_gr_ctx *gr_ctx)
{
/*
* map our circ_buf to the context space and store the GPU VA

5
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,7 +31,8 @@ struct nvgpu_gr_ctx;
int gk20a_fecs_trace_poll(struct gk20a *g);
int gk20a_fecs_trace_init(struct gk20a *g);
int gk20a_fecs_trace_bind_channel(struct gk20a *g,
struct channel_gk20a *ch, struct nvgpu_gr_ctx *gr_ctx);
struct channel_gk20a *ch, u32 vmid,
struct nvgpu_gr_ctx *gr_ctx);
int gk20a_fecs_trace_unbind_channel(struct gk20a *g, struct channel_gk20a *ch);
int gk20a_fecs_trace_reset(struct gk20a *g);
int gk20a_fecs_trace_deinit(struct gk20a *g);

4
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2772,7 +2772,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
}
#ifdef CONFIG_GK20A_CTXSW_TRACE
if (g->ops.fecs_trace.bind_channel && !c->vpr) {
err = g->ops.fecs_trace.bind_channel(g, c, gr_ctx);
err = g->ops.fecs_trace.bind_channel(g, c, 0, gr_ctx);
if (err != 0) {
nvgpu_warn(g,
"fail to bind channel for ctxsw trace");
@@ -2797,7 +2797,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
}
#ifdef CONFIG_GK20A_CTXSW_TRACE
if (g->ops.fecs_trace.bind_channel && !c->vpr) {
err = g->ops.fecs_trace.bind_channel(g, c, gr_ctx);
err = g->ops.fecs_trace.bind_channel(g, c, 0, gr_ctx);
if (err != 0) {
nvgpu_warn(g,
"fail to bind channel for ctxsw trace");

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1044,7 +1044,7 @@ struct gpu_ops {
bool (*is_enabled)(struct gk20a *g);
int (*reset)(struct gk20a *g);
int (*bind_channel)(struct gk20a *g, struct channel_gk20a *ch,
struct nvgpu_gr_ctx *gr_ctx);
u32 vmid, struct nvgpu_gr_ctx *gr_ctx);
int (*unbind_channel)(struct gk20a *g,
struct channel_gk20a *ch);
int (*deinit)(struct gk20a *g);