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gpu: nvgpu: gv11b: fix stall interrupt enablement

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Currently priv, pbus and ltc interrupts are enabled as non-stall but
being handled in stall isr. Fix is to configure them as stall interrupt.

Change-Id: I86adc04f480d5f4befe7e9255b582ce13fa4efc1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1319018
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Seema Khowala
2017-03-10 12:18:40 -08:00
committed by mobile promotions
parent a29521e8d8
commit d5fe11091b
1 changed files with 5 additions and 5 deletions
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10
drivers/gpu/nvgpu/gv11b/mc_gv11b.c
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@@ -30,8 +30,11 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffff);
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f()
| eng_intr_mask;
mc_intr_pfifo_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
mc_intr_ltc_pending_f() |
eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
@@ -39,9 +42,6 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
0xffffffff);
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f()
| mc_intr_priv_ring_pending_f()
| mc_intr_ltc_pending_f()
| mc_intr_pbus_pending_f()
| eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);