gpu: nvgpu: Separate timer from bus

Code touching timer registers was combined with bus code. They're two
logically separate register spaces, so separate the code accordingly.

JIRA NVGPU-588

Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730893
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -23,9 +23,10 @@ obj-$(CONFIG_GK20A) := nvgpu.o
 # OS independent parts of nvgpu. The work to collect files here
 # is in progress.
 
-nvgpu-y += common/bus/bus.o \
-	common/bus/bus_gk20a.o \
-	common/bus/bus_gm20b.o
+nvgpu-y += common/bus/bus_gk20a.o \
+	common/bus/bus_gm20b.o \
+	common/ptimer/ptimer.o \
+	common/ptimer/ptimer_gk20a.o
 
 nvgpu-y += \
 	common/linux/kmem.o \

drivers/gpu/nvgpu/clk/clk_arb.c

@@ -759,7 +759,7 @@ static void nvgpu_clk_arb_run_arbiter_cb(struct nvgpu_clk_arb *arb)
 		goto exit_arb;
 
 #ifdef CONFIG_DEBUG_FS
-	g->ops.bus.read_ptimer(g, &t0);
+	g->ops.ptimer.read_ptimer(g, &t0);
 #endif
 
 	/* Only one arbiter should be running */
@@ -958,7 +958,7 @@ static void nvgpu_clk_arb_run_arbiter_cb(struct nvgpu_clk_arb *arb)
 	nvgpu_cond_signal_interruptible(&arb->request_wq);
 
 #ifdef CONFIG_DEBUG_FS
-	g->ops.bus.read_ptimer(g, &t1);
+	g->ops.ptimer.read_ptimer(g, &t1);
 
 	debug = arb->debug == &arb->debug_pool[0] ?
 		&arb->debug_pool[1] : &arb->debug_pool[0];

drivers/gpu/nvgpu/common/bus/bus_gk20a.c

@@ -28,7 +28,6 @@
 #include "bus_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
 
 void gk20a_bus_init_hw(struct gk20a *g)
 {
@@ -45,7 +44,7 @@ void gk20a_bus_init_hw(struct gk20a *g)
 
 void gk20a_bus_isr(struct gk20a *g)
 {
-	u32 val, save0, save1, fecs_errcode = 0;
+	u32 val;
 
 	val = gk20a_readl(g, bus_intr_0_r());
 
@@ -53,80 +52,13 @@ void gk20a_bus_isr(struct gk20a *g)
 			bus_intr_0_pri_fecserr_m() |
 			bus_intr_0_pri_timeout_m())) {
 
-		save0 = gk20a_readl(g, timer_pri_timeout_save_0_r());
-		if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) {
-			/*
-			 * write & addr fields in timeout_save0
-			 * might not be reliable
-			 */
-			fecs_errcode = gk20a_readl(g,
-					timer_pri_timeout_fecs_errcode_r());
-		}
-
-		save1 = gk20a_readl(g, timer_pri_timeout_save_1_r());
-		nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x "
-			"%s  DATA 0x%08x ",
-			val,
-			timer_pri_timeout_save_0_addr_v(save0) << 2,
-			timer_pri_timeout_save_0_write_v(save0) ?
-			"WRITE" : "READ", save1);
-
-		gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
-		gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
-
-		if (fecs_errcode) {
-			nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode);
-			if (g->ops.priv_ring.decode_error_code)
-				g->ops.priv_ring.decode_error_code(g,
-							fecs_errcode);
-		}
-
+		g->ops.ptimer.isr(g);
 	} else {
 		nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val);
 	}
 	gk20a_writel(g, bus_intr_0_r(), val);
 }
 
-int gk20a_read_ptimer(struct gk20a *g, u64 *value)
-{
-	const unsigned int max_iterations = 3;
-	unsigned int i = 0;
-	u32 gpu_timestamp_hi_prev = 0;
-
-	if (!value)
-		return -EINVAL;
-
-	/* Note. The GPU nanosecond timer consists of two 32-bit
-	 * registers (high & low). To detect a possible low register
-	 * wrap-around between the reads, we need to read the high
-	 * register before and after low. The wraparound happens
-	 * approximately once per 4 secs. */
-
-	/* get initial gpu_timestamp_hi value */
-	gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r());
-
-	for (i = 0; i < max_iterations; ++i) {
-		u32 gpu_timestamp_hi = 0;
-		u32 gpu_timestamp_lo = 0;
-
-		gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r());
-		gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r());
-
-		if (gpu_timestamp_hi == gpu_timestamp_hi_prev) {
-			*value = (((u64)gpu_timestamp_hi) << 32) |
-				gpu_timestamp_lo;
-			return 0;
-		}
-
-		/* wrap-around detected, retry */
-		gpu_timestamp_hi_prev = gpu_timestamp_hi;
-	}
-
-	/* too many iterations, bail out */
-	nvgpu_err(g, "failed to read ptimer");
-	return -EBUSY;
-}
-
 int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
 {
 	u64 iova = nvgpu_inst_block_addr(g, bar1_inst);

drivers/gpu/nvgpu/common/bus/bus_gk20a.h

@@ -25,13 +25,11 @@
 #include <nvgpu/types.h>
 
 struct gk20a;
-struct gpu_ops;
 struct nvgpu_mem;
 struct nvgpu_sgt;
 struct nvgpu_sgl;
 
 void gk20a_bus_isr(struct gk20a *g);
-int gk20a_read_ptimer(struct gk20a *g, u64 *value);
 void gk20a_bus_init_hw(struct gk20a *g);
 int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst);
 u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem,

drivers/gpu/nvgpu/common/bus/bus_gm20b.c

@@ -23,13 +23,10 @@
  */
 
 #include <nvgpu/timers.h>
-#include <nvgpu/bus.h>
 #include <nvgpu/mm.h>
 #include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
-
-#include "bus_gk20a.h"
 #include "bus_gm20b.h"
 
 #include <nvgpu/hw/gm20b/hw_bus_gm20b.h>

drivers/gpu/nvgpu/common/bus/bus_gm20b.h

@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GM20B_BUS
-#define _NVGPU_GM20B_BUS
+#ifndef NVGPU_GM20B_BUS
+#define NVGPU_GM20B_BUS
 
 struct gk20a;
 struct nvgpu_mem;

drivers/gpu/nvgpu/common/linux/ctxsw_trace.c

@@ -702,7 +702,7 @@ void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch)
 	if (!g->ctxsw_trace)
 		return;
 
-	g->ops.bus.read_ptimer(g, &entry.timestamp);
+	g->ops.ptimer.read_ptimer(g, &entry.timestamp);
 	gk20a_ctxsw_trace_write(g, &entry);
 	gk20a_ctxsw_trace_wake_up(g, 0);
 #endif
@@ -722,7 +722,7 @@ void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg)
 	if (!g->ctxsw_trace)
 		return;
 
-	g->ops.bus.read_ptimer(g, &entry.timestamp);
+	g->ops.ptimer.read_ptimer(g, &entry.timestamp);
 	gk20a_ctxsw_trace_write(g, &entry);
 	gk20a_ctxsw_trace_wake_up(g, 0);
 #endif

drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c

@@ -24,7 +24,7 @@
 #include <nvgpu/bitops.h>
 #include <nvgpu/kmem.h>
 #include <nvgpu/bug.h>
-#include <nvgpu/bus.h>
+#include <nvgpu/ptimer.h>
 #include <nvgpu/vidmem.h>
 #include <nvgpu/log.h>
 #include <nvgpu/enabled.h>
@@ -811,7 +811,7 @@ static int nvgpu_gpu_get_cpu_time_correlation_info(
 		return -ENOMEM;
 	}
 
-	err = g->ops.bus.get_timestamps_zipper(g,
+	err = g->ops.ptimer.get_timestamps_zipper(g,
 			args->source_id, args->count, samples);
 	if (!err) {
 		for (i = 0; i < args->count; i++) {
@@ -836,7 +836,7 @@ static int nvgpu_gpu_get_gpu_time(
 	if (err)
 		return err;
 
-	err = g->ops.bus.read_ptimer(g, &time);
+	err = g->ops.ptimer.read_ptimer(g, &time);
 	if (!err)
 		args->gpu_timestamp = time;
 

drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c

@@ -27,7 +27,6 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/debug.h>
-#include <nvgpu/bus.h>
 #include <nvgpu/soc.h>
 #include <nvgpu/ctxsw_trace.h>
 #include <nvgpu/defaults.h>

drivers/gpu/nvgpu/common/ptimer/ptimer.c

@@ -20,7 +20,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <nvgpu/bus.h>
+#include <nvgpu/ptimer.h>
 
 #include "gk20a/gk20a.h"
 
@@ -38,7 +38,7 @@ int nvgpu_get_timestamps_zipper(struct gk20a *g,
 	}
 
 	for (i = 0; i < count; i++) {
-		err = g->ops.bus.read_ptimer(g, &samples[i].gpu_timestamp);
+		err = g->ops.ptimer.read_ptimer(g, &samples[i].gpu_timestamp);
 		if (err)
 			return err;
 

drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+
+#include "gk20a/gk20a.h"
+#include "ptimer_gk20a.h"
+
+#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
+
+void gk20a_ptimer_isr(struct gk20a *g)
+{
+	u32 save0, save1, fecs_errcode = 0;
+
+	save0 = gk20a_readl(g, timer_pri_timeout_save_0_r());
+	if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) {
+		/*
+		 * write & addr fields in timeout_save0
+		 * might not be reliable
+		 */
+		fecs_errcode = gk20a_readl(g,
+				timer_pri_timeout_fecs_errcode_r());
+	}
+
+	save1 = gk20a_readl(g, timer_pri_timeout_save_1_r());
+	nvgpu_err(g, "PRI timeout: ADR 0x%08x "
+		"%s  DATA 0x%08x",
+		timer_pri_timeout_save_0_addr_v(save0) << 2,
+		timer_pri_timeout_save_0_write_v(save0) ?
+		"WRITE" : "READ", save1);
+
+	gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
+	gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
+
+	if (fecs_errcode) {
+		nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode);
+		if (g->ops.priv_ring.decode_error_code)
+			g->ops.priv_ring.decode_error_code(g,
+						fecs_errcode);
+	}
+}
+
+int gk20a_read_ptimer(struct gk20a *g, u64 *value)
+{
+	const unsigned int max_iterations = 3;
+	unsigned int i = 0;
+	u32 gpu_timestamp_hi_prev = 0;
+
+	if (!value)
+		return -EINVAL;
+
+	/* Note. The GPU nanosecond timer consists of two 32-bit
+	 * registers (high & low). To detect a possible low register
+	 * wrap-around between the reads, we need to read the high
+	 * register before and after low. The wraparound happens
+	 * approximately once per 4 secs. */
+
+	/* get initial gpu_timestamp_hi value */
+	gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r());
+
+	for (i = 0; i < max_iterations; ++i) {
+		u32 gpu_timestamp_hi = 0;
+		u32 gpu_timestamp_lo = 0;
+
+		gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r());
+		gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r());
+
+		if (gpu_timestamp_hi == gpu_timestamp_hi_prev) {
+			*value = (((u64)gpu_timestamp_hi) << 32) |
+				gpu_timestamp_lo;
+			return 0;
+		}
+
+		/* wrap-around detected, retry */
+		gpu_timestamp_hi_prev = gpu_timestamp_hi;
+	}
+
+	/* too many iterations, bail out */
+	nvgpu_err(g, "failed to read ptimer");
+	return -EBUSY;
+}

drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef PTIMER_GK20A_H
+#define PTIMER_GK20A_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void gk20a_ptimer_isr(struct gk20a *g);
+int gk20a_read_ptimer(struct gk20a *g, u64 *value);
+
+#endif /* PTIMER_GK20A_H */

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -1120,16 +1120,20 @@ struct gpu_ops {
 	struct {
 		void (*init_hw)(struct gk20a *g);
 		void (*isr)(struct gk20a *g);
-		int (*read_ptimer)(struct gk20a *g, u64 *value);
-		int (*get_timestamps_zipper)(struct gk20a *g,
-			u32 source_id, u32 count,
-			struct nvgpu_cpu_time_correlation_sample *);
 		int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
 		u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem,
 			struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl,
 			u32 w);
 	} bus;
 
+	struct {
+		void (*isr)(struct gk20a *g);
+		int (*read_ptimer)(struct gk20a *g, u64 *value);
+		int (*get_timestamps_zipper)(struct gk20a *g,
+			u32 source_id, u32 count,
+			struct nvgpu_cpu_time_correlation_sample *);
+	} ptimer;
+
 	struct {
 		int (*init)(struct gk20a *g);
 		int (*preos_wait_for_halt)(struct gk20a *g);

drivers/gpu/nvgpu/gm20b/clk_gm20b.c

@@ -32,7 +32,6 @@
 #include <nvgpu/types.h>
 
 #include <nvgpu/hw/gm20b/hw_trim_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_timer_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_therm_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
 

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -25,6 +25,7 @@
 #include "common/clock_gating/gm20b_gating_reglist.h"
 #include "common/bus/bus_gm20b.h"
 #include "common/bus/bus_gk20a.h"
+#include "common/ptimer/ptimer_gk20a.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/ce2_gk20a.h"
@@ -60,7 +61,7 @@
 #include <nvgpu/debug.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/enabled.h>
-#include <nvgpu/bus.h>
+#include <nvgpu/ptimer.h>
 #include <nvgpu/error_notifier.h>
 
 #include <nvgpu/hw/gm20b/hw_proj_gm20b.h>
@@ -605,11 +606,14 @@ static const struct gpu_ops gm20b_ops = {
 	.bus = {
 		.init_hw = gk20a_bus_init_hw,
 		.isr = gk20a_bus_isr,
-		.read_ptimer = gk20a_read_ptimer,
-		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
 		.bar1_bind = gm20b_bus_bar1_bind,
 		.set_bar0_window = gk20a_bus_set_bar0_window,
 	},
+	.ptimer = {
+		.isr = gk20a_ptimer_isr,
+		.read_ptimer = gk20a_read_ptimer,
+		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+	},
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	.css = {
 		.enable_snapshot = css_hw_enable_snapshot,
@@ -667,6 +671,7 @@ int gm20b_init_hal(struct gk20a *g)
 	gops->debug = gm20b_ops.debug;
 	gops->debugger = gm20b_ops.debugger;
 	gops->bus = gm20b_ops.bus;
+	gops->ptimer = gm20b_ops.ptimer;
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	gops->css = gm20b_ops.css;
 #endif

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -24,6 +24,7 @@
 
 #include "common/bus/bus_gk20a.h"
 #include "common/clock_gating/gp106_gating_reglist.h"
+#include "common/ptimer/ptimer_gk20a.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -86,7 +87,7 @@
 
 #include <nvgpu/debug.h>
 #include <nvgpu/bug.h>
-#include <nvgpu/bus.h>
+#include <nvgpu/ptimer.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/ctxsw_trace.h>
 #include <nvgpu/error_notifier.h>
@@ -720,11 +721,14 @@ static const struct gpu_ops gp106_ops = {
 	.bus = {
 		.init_hw = gk20a_bus_init_hw,
 		.isr = gk20a_bus_isr,
-		.read_ptimer = gk20a_read_ptimer,
-		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
 		.bar1_bind = gk20a_bus_bar1_bind,
 		.set_bar0_window = gk20a_bus_set_bar0_window,
 	},
+	.ptimer = {
+		.isr = gk20a_ptimer_isr,
+		.read_ptimer = gk20a_read_ptimer,
+		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+	},
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	.css = {
 		.enable_snapshot = css_hw_enable_snapshot,
@@ -806,6 +810,7 @@ int gp106_init_hal(struct gk20a *g)
 	gops->debugger = gp106_ops.debugger;
 	gops->dbg_session_ops = gp106_ops.dbg_session_ops;
 	gops->bus = gp106_ops.bus;
+	gops->ptimer = gp106_ops.ptimer;
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	gops->css = gp106_ops.css;
 #endif

drivers/gpu/nvgpu/gp106/mclk_gp106.c

@@ -3353,7 +3353,7 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
 	pseq_cmd->cmd_type = NV_PMU_SEQ_CMD_ID_RUN_SCRIPT;
 
 #ifdef CONFIG_DEBUG_FS
-	g->ops.bus.read_ptimer(g, &t0);
+	g->ops.ptimer.read_ptimer(g, &t0);
 #endif
 
 	if (speed == GP106_MCLK_HIGH_SPEED) {
@@ -3402,7 +3402,7 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
 	mclk->speed = speed;
 
 #ifdef CONFIG_DEBUG_FS
-	g->ops.bus.read_ptimer(g, &t1);
+	g->ops.ptimer.read_ptimer(g, &t1);
 
 	nvgpu_mutex_acquire(&mclk->data_lock);
 	mclk->switch_num++;

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -24,6 +24,7 @@
 
 #include "common/bus/bus_gk20a.h"
 #include "common/clock_gating/gp10b_gating_reglist.h"
+#include "common/ptimer/ptimer_gk20a.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -69,7 +70,7 @@
 #include <nvgpu/debug.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/enabled.h>
-#include <nvgpu/bus.h>
+#include <nvgpu/ptimer.h>
 #include <nvgpu/ctxsw_trace.h>
 #include <nvgpu/error_notifier.h>
 
@@ -650,11 +651,14 @@ static const struct gpu_ops gp10b_ops = {
 	.bus = {
 		.init_hw = gk20a_bus_init_hw,
 		.isr = gk20a_bus_isr,
-		.read_ptimer = gk20a_read_ptimer,
-		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
 		.bar1_bind = gk20a_bus_bar1_bind,
 		.set_bar0_window = gk20a_bus_set_bar0_window,
 	},
+	.ptimer = {
+		.isr = gk20a_ptimer_isr,
+		.read_ptimer = gk20a_read_ptimer,
+		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+	},
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	.css = {
 		.enable_snapshot = css_hw_enable_snapshot,
@@ -705,6 +709,7 @@ int gp10b_init_hal(struct gk20a *g)
 	gops->debugger = gp10b_ops.debugger;
 	gops->dbg_session_ops = gp10b_ops.dbg_session_ops;
 	gops->bus = gp10b_ops.bus;
+	gops->ptimer = gp10b_ops.ptimer;
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	gops->css = gp10b_ops.css;
 #endif

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -24,6 +24,7 @@
 
 #include "common/bus/bus_gk20a.h"
 #include "common/clock_gating/gv100_gating_reglist.h"
+#include "common/ptimer/ptimer_gk20a.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -99,7 +100,7 @@
 #include "gv100/nvlink_gv100.h"
 #include "gv100/regops_gv100.h"
 
-#include <nvgpu/bus.h>
+#include <nvgpu/ptimer.h>
 #include <nvgpu/debug.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/ctxsw_trace.h>
@@ -790,11 +791,14 @@ static const struct gpu_ops gv100_ops = {
 	.bus = {
 		.init_hw = gk20a_bus_init_hw,
 		.isr = gk20a_bus_isr,
-		.read_ptimer = gk20a_read_ptimer,
-		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
 		.bar1_bind = NULL,
 		.set_bar0_window = gk20a_bus_set_bar0_window,
 	},
+	.ptimer = {
+		.isr = gk20a_ptimer_isr,
+		.read_ptimer = gk20a_read_ptimer,
+		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+	},
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	.css = {
 		.enable_snapshot = gv11b_css_hw_enable_snapshot,
@@ -878,6 +882,7 @@ int gv100_init_hal(struct gk20a *g)
 	gops->debugger = gv100_ops.debugger;
 	gops->dbg_session_ops = gv100_ops.dbg_session_ops;
 	gops->bus = gv100_ops.bus;
+	gops->ptimer = gv100_ops.ptimer;
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	gops->css = gv100_ops.css;
 #endif

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -24,6 +24,7 @@
 
 #include "common/bus/bus_gk20a.h"
 #include "common/clock_gating/gv11b_gating_reglist.h"
+#include "common/ptimer/ptimer_gk20a.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -82,7 +83,7 @@
 #include "subctx_gv11b.h"
 #include "therm_gv11b.h"
 
-#include <nvgpu/bus.h>
+#include <nvgpu/ptimer.h>
 #include <nvgpu/debug.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/ctxsw_trace.h>
@@ -722,11 +723,14 @@ static const struct gpu_ops gv11b_ops = {
 	.bus = {
 		.init_hw = gk20a_bus_init_hw,
 		.isr = gk20a_bus_isr,
-		.read_ptimer = gk20a_read_ptimer,
-		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
 		.bar1_bind = NULL,
 		.set_bar0_window = gk20a_bus_set_bar0_window,
 	},
+	.ptimer = {
+		.isr = gk20a_ptimer_isr,
+		.read_ptimer = gk20a_read_ptimer,
+		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+	},
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	.css = {
 		.enable_snapshot = gv11b_css_hw_enable_snapshot,
@@ -776,6 +780,7 @@ int gv11b_init_hal(struct gk20a *g)
 	gops->debugger = gv11b_ops.debugger;
 	gops->dbg_session_ops = gv11b_ops.dbg_session_ops;
 	gops->bus = gv11b_ops.bus;
+	gops->ptimer = gv11b_ops.ptimer;
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	gops->css = gv11b_ops.css;
 #endif

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -523,11 +523,14 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	.bus = {
 		.init_hw = gk20a_bus_init_hw,
 		.isr = gk20a_bus_isr,
-		.read_ptimer = vgpu_read_ptimer,
-		.get_timestamps_zipper = vgpu_get_timestamps_zipper,
 		.bar1_bind = gk20a_bus_bar1_bind,
 		.set_bar0_window = gk20a_bus_set_bar0_window,
 	},
+	.ptimer = {
+		.isr = NULL,
+		.read_ptimer = vgpu_read_ptimer,
+		.get_timestamps_zipper = vgpu_get_timestamps_zipper,
+	},
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	.css = {
 		.enable_snapshot = vgpu_css_enable_snapshot_buffer,
@@ -578,6 +581,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
 	gops->debugger = vgpu_gp10b_ops.debugger;
 	gops->dbg_session_ops = vgpu_gp10b_ops.dbg_session_ops;
 	gops->bus = vgpu_gp10b_ops.bus;
+	gops->ptimer = vgpu_gp10b_ops.ptimer;
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	gops->css = vgpu_gp10b_ops.css;
 #endif

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -574,11 +574,14 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	.bus = {
 		.init_hw = gk20a_bus_init_hw,
 		.isr = gk20a_bus_isr,
-		.read_ptimer = vgpu_read_ptimer,
-		.get_timestamps_zipper = vgpu_get_timestamps_zipper,
 		.bar1_bind = NULL,
 		.set_bar0_window = gk20a_bus_set_bar0_window,
 	},
+	.ptimer = {
+		.isr = NULL,
+		.read_ptimer = vgpu_read_ptimer,
+		.get_timestamps_zipper = vgpu_get_timestamps_zipper,
+	},
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	.css = {
 		.enable_snapshot = vgpu_css_enable_snapshot_buffer,
@@ -625,6 +628,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
 	gops->debugger = vgpu_gv11b_ops.debugger;
 	gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops;
 	gops->bus = vgpu_gv11b_ops.bus;
+	gops->ptimer = vgpu_gv11b_ops.ptimer;
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 	gops->css = vgpu_gv11b_ops.css;
 #endif

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -21,7 +21,7 @@
  */
 
 #include <nvgpu/enabled.h>
-#include <nvgpu/bus.h>
+#include <nvgpu/ptimer.h>
 #include <nvgpu/vgpu/vgpu_ivc.h>
 #include <nvgpu/vgpu/vgpu.h>