gpu: nvgpu: prepare class unit for safety build

Move graphics related defs and functions under CONFIG_NVGPU_GRAPHICS
switch.
Move classes not supported in GV11B under CONFIG_NVGPU_NON_FUSA
switch.
Add missing valid class numbers to gpu_class.is_valid HAL.
Also remove un-used class defs from class.h header.

Lot of qnx safety tests are still using graphics 3d class.
Until those tests got fixed, allowing 3d graphics class
as valid class for safety build.

JIRA NVGPU-4301

Change-Id: Ifd2a13bee3210821799c2bca10e7245eb3c79121
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224658
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/obj_ctx.c

@@ -184,8 +184,11 @@ static int nvgpu_gr_obj_ctx_set_compute_preemption_mode(struct gk20a *g,
 	struct nvgpu_gr_ctx *gr_ctx, u32 class_num, u32 compute_preempt_mode)
 {
 
-	if (g->ops.gpu_class.is_valid_compute(class_num) ||
+	if (g->ops.gpu_class.is_valid_compute(class_num)
-			g->ops.gpu_class.is_valid_gfx(class_num)) {
+#ifdef CONFIG_NVGPU_GRAPHICS
+		|| g->ops.gpu_class.is_valid_gfx(class_num)
+#endif
+		) {
 		switch (compute_preempt_mode) {
 		case NVGPU_PREEMPTION_MODE_COMPUTE_WFI:
 		case NVGPU_PREEMPTION_MODE_COMPUTE_CTA:

drivers/gpu/nvgpu/hal/class/class_gm20b_fusa.c

@@ -29,14 +29,24 @@ bool gm20b_class_is_valid(u32 class_num)
 	bool valid;
 
 	switch (class_num) {
-	case MAXWELL_COMPUTE_B:
-	case MAXWELL_B:
-	case FERMI_TWOD_A:
 	case KEPLER_DMA_COPY_A:
+	case KEPLER_INLINE_TO_MEMORY_B:
 	case MAXWELL_DMA_COPY_A:
+	case MAXWELL_CHANNEL_GPFIFO_A:
 		valid = true;
 		break;
 
+#ifdef CONFIG_NVGPU_NON_FUSA
+	case MAXWELL_COMPUTE_B:
+		valid = true;
+		break;
+#endif
+#ifdef CONFIG_NVGPU_GRAPHICS
+	case MAXWELL_B:
+	case FERMI_TWOD_A:
+		valid = true;
+		break;
+#endif
 	default:
 		valid = false;
 		break;

drivers/gpu/nvgpu/hal/class/class_gp10b.h

@@ -26,7 +26,10 @@
 #include <nvgpu/types.h>
 
 bool gp10b_class_is_valid(u32 class_num);
-bool gp10b_class_is_valid_gfx(u32 class_num);
 bool gp10b_class_is_valid_compute(u32 class_num);
 
+#ifdef CONFIG_NVGPU_GRAPHICS
+bool gp10b_class_is_valid_gfx(u32 class_num);
+#endif
+
 #endif /* NVGPU_CLASS_GP10B */

drivers/gpu/nvgpu/hal/class/class_gp10b_fusa.c

@@ -32,11 +32,20 @@ bool gp10b_class_is_valid(u32 class_num)
 
 	nvgpu_speculation_barrier();
 	switch (class_num) {
-	case PASCAL_COMPUTE_A:
-	case PASCAL_A:
 	case PASCAL_DMA_COPY_A:
+	case PASCAL_CHANNEL_GPFIFO_A:
 		valid = true;
 		break;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	case PASCAL_A:
+		valid = true;
+		break;
+#endif
+#ifdef CONFIG_NVGPU_NON_FUSA
+	case PASCAL_COMPUTE_A:
+		valid = true;
+		break;
+#endif
 	default:
 		valid = gm20b_class_is_valid(class_num);
 		break;
@@ -44,6 +53,7 @@ bool gp10b_class_is_valid(u32 class_num)
 	return valid;
 }
 
+#ifdef CONFIG_NVGPU_GRAPHICS
 bool gp10b_class_is_valid_gfx(u32 class_num)
 {
 	if (class_num == PASCAL_A ||  class_num == MAXWELL_B) {
@@ -52,7 +62,9 @@ bool gp10b_class_is_valid_gfx(u32 class_num)
 		return false;
 	}
 }
+#endif
 
+#ifdef CONFIG_NVGPU_NON_FUSA
 bool gp10b_class_is_valid_compute(u32 class_num)
 {
 	if (class_num == PASCAL_COMPUTE_A ||  class_num == MAXWELL_COMPUTE_B) {
@@ -61,3 +73,4 @@ bool gp10b_class_is_valid_compute(u32 class_num)
 		return false;
 	}
 }
+#endif

drivers/gpu/nvgpu/hal/class/class_gv11b.h

@@ -26,7 +26,10 @@
 #include <nvgpu/types.h>
 
 bool gv11b_class_is_valid(u32 class_num);
-bool gv11b_class_is_valid_gfx(u32 class_num);
 bool gv11b_class_is_valid_compute(u32 class_num);
 
+#ifdef CONFIG_NVGPU_GRAPHICS
+bool gv11b_class_is_valid_gfx(u32 class_num);
+#endif
+
 #endif /* NVGPU_CLASS_GV11B */

drivers/gpu/nvgpu/hal/class/class_gv11b_fusa.c

@@ -33,9 +33,10 @@ bool gv11b_class_is_valid(u32 class_num)
 	nvgpu_speculation_barrier();
 
 	switch (class_num) {
-	case VOLTA_COMPUTE_A:
 	case VOLTA_A:
+	case VOLTA_COMPUTE_A:
 	case VOLTA_DMA_COPY_A:
+	case VOLTA_CHANNEL_GPFIFO_A:
 		valid = true;
 		break;
 	default:
@@ -45,6 +46,7 @@ bool gv11b_class_is_valid(u32 class_num)
 	return valid;
 }
 
+#ifdef CONFIG_NVGPU_GRAPHICS
 bool gv11b_class_is_valid_gfx(u32 class_num)
 {
 	bool valid;
@@ -61,21 +63,13 @@ bool gv11b_class_is_valid_gfx(u32 class_num)
 	}
 	return valid;
 }
+#endif
 
 bool gv11b_class_is_valid_compute(u32 class_num)
 {
-	bool valid;
+	if (class_num == VOLTA_COMPUTE_A) {
-
+		return true;
-	nvgpu_speculation_barrier();
+	} else {
-
+		return false;
-	switch (class_num) {
-	case VOLTA_COMPUTE_A:
-		valid = true;
-		break;
-
-	default:
-		valid = gp10b_class_is_valid_compute(class_num);
-		break;
 	}
-	return valid;
 }

drivers/gpu/nvgpu/hal/class/class_tu104.c

@@ -34,9 +34,11 @@ bool tu104_class_is_valid(u32 class_num)
 
 	switch (class_num) {
 	case TURING_CHANNEL_GPFIFO_A:
-	case TURING_A:
 	case TURING_COMPUTE_A:
 	case TURING_DMA_COPY_A:
+#ifdef CONFIG_NVGPU_GRAPHICS
+	case TURING_A:
+#endif
 		valid = true;
 		break;
 	default:
@@ -46,6 +48,7 @@ bool tu104_class_is_valid(u32 class_num)
 	return valid;
 };
 
+#ifdef CONFIG_NVGPU_GRAPHICS
 bool tu104_class_is_valid_gfx(u32 class_num)
 {
 	bool valid;
@@ -62,6 +65,7 @@ bool tu104_class_is_valid_gfx(u32 class_num)
 	}
 	return valid;
 }
+#endif
 
 bool tu104_class_is_valid_compute(u32 class_num)
 {

drivers/gpu/nvgpu/hal/class/class_tu104.h

@@ -26,7 +26,10 @@
 #include <nvgpu/types.h>
 
 bool tu104_class_is_valid(u32 class_num);
-bool tu104_class_is_valid_gfx(u32 class_num);
 bool tu104_class_is_valid_compute(u32 class_num);
 
+#ifdef CONFIG_NVGPU_GRAPHICS
+bool tu104_class_is_valid_gfx(u32 class_num);
+#endif
+
 #endif /* NVGPU_CLASS_TU104 */

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c

@@ -46,6 +46,7 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 
 	nvgpu_log_fn(g, " ");
 
+#ifdef CONFIG_NVGPU_NON_FUSA
 	if (class_num == MAXWELL_COMPUTE_B) {
 		switch (offset << 2) {
 		case NVB1C0_SET_SHADER_EXCEPTIONS:
@@ -59,6 +60,7 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			break;
 		}
 	}
+#endif
 
 	if (ret != 0) {
 		goto fail;

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c

@@ -44,6 +44,7 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 
 	nvgpu_log_fn(g, " ");
 
+#ifdef CONFIG_NVGPU_NON_FUSA
 	if (class_num == PASCAL_COMPUTE_A) {
 		switch (offset << 2) {
 		case NVC0C0_SET_SHADER_EXCEPTIONS:
@@ -57,6 +58,7 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			break;
 		}
 	}
+#endif
 
 	if (ret != 0) {
 		goto fail;

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -556,8 +556,10 @@ static const struct gpu_ops gm20b_ops = {
 	},
 	.gpu_class = {
 		.is_valid = gm20b_class_is_valid,
-		.is_valid_gfx = gm20b_class_is_valid_gfx,
 		.is_valid_compute = gm20b_class_is_valid_compute,
+#ifdef CONFIG_NVGPU_GRAPHICS
+		.is_valid_gfx = gm20b_class_is_valid_gfx,
+#endif
 	},
 	.fb = {
 		.init_hw = gm20b_fb_init_hw,

drivers/gpu/nvgpu/hal/init/hal_gm20b_litter.c

@@ -111,15 +111,19 @@ u32 gm20b_get_litter_value(struct gk20a *g, int value)
 	case GPU_LIT_FBPA_SHARED_BASE:
 		ret = 0;
 		break;
+#ifdef CONFIG_NVGPU_GRAPHICS
 	case GPU_LIT_TWOD_CLASS:
 		ret = FERMI_TWOD_A;
 		break;
 	case GPU_LIT_THREED_CLASS:
 		ret = MAXWELL_B;
 		break;
+#endif
+#ifdef CONFIG_NVGPU_NON_FUSA
 	case GPU_LIT_COMPUTE_CLASS:
 		ret = MAXWELL_COMPUTE_B;
 		break;
+#endif
 	case GPU_LIT_GPFIFO_CLASS:
 		ret = MAXWELL_CHANNEL_GPFIFO_A;
 		break;

drivers/gpu/nvgpu/hal/init/hal_gp10b_litter.c

@@ -111,15 +111,19 @@ u32 gp10b_get_litter_value(struct gk20a *g, int value)
 	case GPU_LIT_FBPA_SHARED_BASE:
 		ret = 0;
 		break;
+#ifdef CONFIG_NVGPU_GRAPHICS
 	case GPU_LIT_TWOD_CLASS:
 		ret = FERMI_TWOD_A;
 		break;
 	case GPU_LIT_THREED_CLASS:
 		ret = PASCAL_A;
 		break;
+#endif
+#ifdef CONFIG_NVGPU_NON_FUSA
 	case GPU_LIT_COMPUTE_CLASS:
 		ret = PASCAL_COMPUTE_A;
 		break;
+#endif
 	case GPU_LIT_GPFIFO_CLASS:
 		ret = PASCAL_CHANNEL_GPFIFO_A;
 		break;

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -766,8 +766,10 @@ static const struct gpu_ops gv11b_ops = {
 	},
 	.gpu_class = {
 		.is_valid = gv11b_class_is_valid,
-		.is_valid_gfx = gv11b_class_is_valid_gfx,
 		.is_valid_compute = gv11b_class_is_valid_compute,
+#ifdef CONFIG_NVGPU_GRAPHICS
+		.is_valid_gfx = gv11b_class_is_valid_gfx,
+#endif
 	},
 	.fb = {
 #ifdef CONFIG_NVGPU_INJECT_HWERR

drivers/gpu/nvgpu/hal/init/hal_gv11b_litter.c

@@ -126,12 +126,14 @@ u32 gv11b_get_litter_value(struct gk20a *g, int value)
 	case GPU_LIT_FBPA_SHARED_BASE:
 		ret = 0;
 		break;
+#ifdef CONFIG_NVGPU_GRAPHICS
 	case GPU_LIT_TWOD_CLASS:
 		ret = FERMI_TWOD_A;
 		break;
 	case GPU_LIT_THREED_CLASS:
 		ret = VOLTA_A;
 		break;
+#endif
 	case GPU_LIT_COMPUTE_CLASS:
 		ret = VOLTA_COMPUTE_A;
 		break;

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -786,8 +786,10 @@ static const struct gpu_ops tu104_ops = {
 	},
 	.gpu_class = {
 		.is_valid = tu104_class_is_valid,
-		.is_valid_gfx = tu104_class_is_valid_gfx,
 		.is_valid_compute = tu104_class_is_valid_compute,
+#ifdef CONFIG_NVGPU_GRAPHICS
+		.is_valid_gfx = tu104_class_is_valid_gfx,
+#endif
 	},
 	.fb = {
 		.init_hw = gv11b_fb_init_hw,

drivers/gpu/nvgpu/hal/init/hal_tu104_litter.c

@@ -125,24 +125,30 @@ u32 tu104_get_litter_value(struct gk20a *g, int value)
 	case GPU_LIT_SMPC_PRI_STRIDE:
 		ret = proj_smpc_stride_v();
 		break;
+#ifdef CONFIG_NVGPU_GRAPHICS
 	case GPU_LIT_TWOD_CLASS:
 		ret = FERMI_TWOD_A;
 		break;
 	case GPU_LIT_THREED_CLASS:
 		ret = TURING_A;
 		break;
+#endif
+#ifdef CONFIG_NVGPU_NON_FUSA
 	case GPU_LIT_COMPUTE_CLASS:
 		ret = TURING_COMPUTE_A;
 		break;
 	case GPU_LIT_GPFIFO_CLASS:
 		ret = TURING_CHANNEL_GPFIFO_A;
 		break;
+#endif
 	case GPU_LIT_I2M_CLASS:
 		ret = KEPLER_INLINE_TO_MEMORY_B;
 		break;
+#ifdef CONFIG_NVGPU_NON_FUSA
 	case GPU_LIT_DMA_COPY_CLASS:
 		ret = TURING_DMA_COPY_A;
 		break;
+#endif
 	case GPU_LIT_GPC_PRIV_STRIDE:
 		ret = proj_gpc_priv_stride_v();
 		break;

drivers/gpu/nvgpu/include/nvgpu/class.h

@@ -23,33 +23,33 @@
 #ifndef NVGPU_CLASS_H
 #define NVGPU_CLASS_H
 
-#define	FERMI_TWOD_A			0x902DU
-#define	KEPLER_INLINE_TO_MEMORY_A	0xA040U
 #define	KEPLER_DMA_COPY_A		0xA0B5U
-
-#define	MAXWELL_B			0xB197U
-#define	MAXWELL_COMPUTE_B		0xB1C0U
 #define	KEPLER_INLINE_TO_MEMORY_B	0xA140U
+
 #define	MAXWELL_DMA_COPY_A		0xB0B5U
 #define	MAXWELL_CHANNEL_GPFIFO_A	0xB06FU
 
 #define	PASCAL_CHANNEL_GPFIFO_A		0xC06FU
-#define	PASCAL_A			0xC097U
-#define	PASCAL_COMPUTE_A		0xC0C0U
 #define	PASCAL_DMA_COPY_A		0xC0B5U
-#define	PASCAL_DMA_COPY_B		0xC1B5U
 
-#define PASCAL_B		0xC197U
+#define	VOLTA_A				0xC397U
-#define	PASCAL_COMPUTE_B	0xC1C0U
+#define	VOLTA_CHANNEL_GPFIFO_A		0xC36FU
+#define	VOLTA_COMPUTE_A			0xC3C0U
+#define	VOLTA_DMA_COPY_A		0xC3B5U
 
-#define	VOLTA_CHANNEL_GPFIFO_A	0xC36FU
+#ifdef CONFIG_NVGPU_GRAPHICS
-#define	VOLTA_A			0xC397U
+#define	FERMI_TWOD_A			0x902DU
-#define	VOLTA_COMPUTE_A		0xC3C0U
+#define	MAXWELL_B			0xB197U
-#define	VOLTA_DMA_COPY_A	0xC3B5U
+#define	PASCAL_A			0xC097U
+#define	TURING_A			0xC597U
+#endif
 
-#define	TURING_CHANNEL_GPFIFO_A	0xC46FU
+#ifdef CONFIG_NVGPU_NON_FUSA
-#define	TURING_A		0xC597U
+#define	MAXWELL_COMPUTE_B		0xB1C0U
-#define	TURING_COMPUTE_A	0xC5C0U
+#define	PASCAL_COMPUTE_A		0xC0C0U
-#define	TURING_DMA_COPY_A	0xC5B5U
+#define	TURING_CHANNEL_GPFIFO_A		0xC46FU
+#define	TURING_COMPUTE_A		0xC5C0U
+#define	TURING_DMA_COPY_A		0xC5B5U
+#endif
 
 #endif /* NVGPU_CLASS_H */

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -284,8 +284,10 @@ struct gpu_ops {
 	struct gops_gr gr;
 	struct {
 		bool (*is_valid)(u32 class_num);
-		bool (*is_valid_gfx)(u32 class_num);
 		bool (*is_valid_compute)(u32 class_num);
+#ifdef CONFIG_NVGPU_GRAPHICS
+		bool (*is_valid_gfx)(u32 class_num);
+#endif
 	} gpu_class;
 
 	struct gops_fb fb;

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -330,8 +330,10 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 	gpu.reg_ops_limit = NVGPU_IOCTL_DBG_REG_OPS_LIMIT;
 	gpu.map_buffer_batch_limit = nvgpu_is_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH) ?
 		NVGPU_IOCTL_AS_MAP_BUFFER_BATCH_LIMIT : 0;
+#ifdef CONFIG_NVGPU_GRAPHICS
 	gpu.twod_class = g->ops.get_litter_value(g, GPU_LIT_TWOD_CLASS);
 	gpu.threed_class = g->ops.get_litter_value(g, GPU_LIT_THREED_CLASS);
+#endif
 	gpu.compute_class = g->ops.get_litter_value(g, GPU_LIT_COMPUTE_CLASS);
 	gpu.gpfifo_class = g->ops.get_litter_value(g, GPU_LIT_GPFIFO_CLASS);
 	gpu.inline_to_memory_class =