nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add clear_sm_hww gr ops

Browse Source 
Required for multiple SM support and t19x SM
register address changes

JIRA GPUT19X-75

Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Seema Khowala
2017-06-22 13:43:35 -07:00
committed by mobile promotions
parent 0852c9f1ab
commit d8c0144f8b
5 changed files with 21 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -300,6 +300,8 @@ struct gpu_ops {
u32 global_esr_mask, bool check_errors);
int (*wait_for_sm_lock_down)(struct gk20a *g, u32 gpc, u32 tpc,
u32 sm, u32 global_esr_mask, bool check_errors);
void (*clear_sm_hww)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
u32 global_esr);
void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel);
int (*handle_sm_exception)(struct gk20a *g,

21
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -5501,21 +5501,6 @@ bool gk20a_gr_sm_debugger_attached(struct gk20a *g)
return false;
}
void gk20a_gr_clear_sm_hww(struct gk20a *g,
u32 gpc, u32 tpc, u32 global_esr)
{
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
global_esr);
/* clear the warp hww */
gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset,
gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f());
}
int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr)
@@ -5678,7 +5663,8 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
/* clear the hwws, also causes tpc and gpc
* exceptions to be cleared
*/
gk20a_gr_clear_sm_hww(g, gpc, tpc, *hww_global_esr);
g->ops.gr.clear_sm_hww(g,
gpc, tpc, sm, *hww_global_esr);
}
@@ -8439,7 +8425,8 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g)
/* clearing hwws, also causes tpc and gpc
* exceptions to be cleared
*/
gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr);
g->ops.gr.clear_sm_hww(g,
gpc, tpc, sm, global_esr);
}
}
}

4
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -539,8 +539,6 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config);
/* sm */
bool gk20a_gr_sm_debugger_attached(struct gk20a *g);
void gk20a_gr_clear_sm_hww(struct gk20a *g,
u32 gpc, u32 tpc, u32 global_esr);
u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
#define gr_gk20a_elpg_protected_call(g, func) \
@@ -683,8 +681,6 @@ int gk20a_gr_lock_down_sm(struct gk20a *g,
bool check_errors);
int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
u32 global_esr_mask, bool check_errors);
void gk20a_gr_clear_sm_hww(struct gk20a *g,
u32 gpc, u32 tpc, u32 global_esr);
int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
u32 *mailbox_ret, u32 opc_success,
u32 mailbox_ok, u32 opc_fail,

13
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -1530,6 +1530,18 @@ static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
priv_addr_table, priv_addr_table_index);
}
static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
u32 global_esr)
{
u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc);
gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
global_esr);
/* clear the warp hww */
gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0);
}
void gm20b_init_gr(struct gpu_ops *gops)
{
gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu;
@@ -1640,4 +1652,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask;
gops->gr.lock_down_sm = gk20a_gr_lock_down_sm;
gops->gr.wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down;
gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww;
}

3
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -1835,7 +1835,8 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
/* reset the HWW errors after locking down */
global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g,
gpc, tpc, sm);
gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy);
g->ops.gr.clear_sm_hww(g,
gpc, tpc, sm, global_esr_copy);
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
"CILP: HWWs cleared for gpc %d tpc %d\n",
gpc, tpc);