nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: fix gpc/tpc index for SMPC broadcast conversion

Browse Source 
In gv11b_gr_egpc_etpc_priv_addr_table(), we call
gv11b_gr_update_priv_addr_table_smpc() to convert SMPC broadcast address into
list of unicast addresses

But before calling gv11b_gr_update_priv_addr_table_smpc() we sometimes
incorrectly set gpc_num/tpc_num to zero and that leads to generating incorrect
list of unicast addresses

Remove this incorrect initialization of gpc_num/tpc_num

Also update gv11b_gr_egpc_etpc_priv_addr_table() to receive tpc_num along with
gpc_num

Bug 2099717
Jira NVGPU-580

Change-Id: Idd4e5f78dbe6ca1800efae93c66355d06417d1f2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1691373
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-04-09 19:56:59 +05:30
committed by mobile promotions
parent aa1f8e01ce
commit d91ea322e1
4 changed files with 9 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -244,7 +244,8 @@ struct gpu_ops {
u32 addr, int *addr_type,
u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags);
void (*egpc_etpc_priv_addr_table)(struct gk20a *g, u32 addr,
u32 gpc, u32 broadcast_flags, u32 *priv_addr_table,
u32 gpc, u32 tpc, u32 broadcast_flags,
u32 *priv_addr_table,
u32 *priv_addr_table_index);
bool (*is_tpc_addr)(struct gk20a *g, u32 addr);
bool (*is_egpc_addr)(struct gk20a *g, u32 addr);

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -6421,7 +6421,7 @@ int gr_gk20a_create_priv_addr_table(struct gk20a *g,
(addr_type == CTXSW_ADDR_TYPE_ETPC)) &&
g->ops.gr.egpc_etpc_priv_addr_table) {
gk20a_dbg(gpu_dbg_gpu_dbg, "addr_type : EGPC/ETPC");
g->ops.gr.egpc_etpc_priv_addr_table(g, addr, gpc_num,
g->ops.gr.egpc_etpc_priv_addr_table(g, addr, gpc_num, tpc_num,
broadcast_flags, priv_addr_table, &t);
} else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTSS) {
g->ops.gr.split_lts_broadcast_addr(g, addr,

14
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -4018,9 +4018,9 @@ static void gv11b_gr_update_priv_addr_table_smpc(struct gk20a *g, u32 gpc_num,
}
void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t)
u32 gpc_num, u32 tpc_num, u32 broadcast_flags,
u32 *priv_addr_table, u32 *t)
{
u32 gpc_num, tpc_num;
u32 priv_addr, gpc_addr;
nvgpu_log_info(g, "addr=0x%x", addr);
@@ -4055,7 +4055,6 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
}
}
} else if (broadcast_flags & PRI_BROADCAST_FLAGS_SMPC) {
tpc_num = 0;
gv11b_gr_update_priv_addr_table_smpc(
g, gpc_num, tpc_num, addr,
priv_addr_table, t);
@@ -4078,9 +4077,8 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
} else if (!(broadcast_flags & PRI_BROADCAST_FLAGS_EGPC)) {
if (broadcast_flags & PRI_BROADCAST_FLAGS_ETPC) {
nvgpu_log_info(g, "broadcast flags etpc but not egpc");
gpc_num = 0;
for (tpc_num = 0;
tpc_num < g->gr.gpc_tpc_count[gpc];
tpc_num < g->gr.gpc_tpc_count[gpc_num];
tpc_num++) {
if (broadcast_flags &
PRI_BROADCAST_FLAGS_SMPC)
@@ -4091,7 +4089,7 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
priv_addr_table[*t] =
pri_etpc_addr(g,
pri_tpccs_addr_mask(addr),
gpc, tpc_num);
gpc_num, tpc_num);
nvgpu_log_info(g,
"priv_addr_table[%d]:%#08x",
*t, priv_addr_table[*t]);
@@ -4099,8 +4097,6 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
}
}
} else if (broadcast_flags & PRI_BROADCAST_FLAGS_SMPC) {
tpc_num = 0;
gpc_num = 0;
gv11b_gr_update_priv_addr_table_smpc(
g, gpc_num, tpc_num, addr,
priv_addr_table, t);
@@ -4666,7 +4662,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
(addr_type == CTXSW_ADDR_TYPE_ETPC)) &&
g->ops.gr.egpc_etpc_priv_addr_table) {
gk20a_dbg(gpu_dbg_gpu_dbg, "addr_type : EGPC/ETPC");
g->ops.gr.egpc_etpc_priv_addr_table(g, addr, gpc_num,
g->ops.gr.egpc_etpc_priv_addr_table(g, addr, gpc_num, tpc_num,
broadcast_flags, priv_addr_table, &t);
} else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTSS) {
g->ops.gr.split_lts_broadcast_addr(g, addr,

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -214,7 +214,7 @@ void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr,
int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type,
u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags);
void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t);
u32 gpc, u32 tpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t);
u32 gv11b_gr_get_egpc_base(struct gk20a *g);
void gr_gv11b_init_gpc_mmu(struct gk20a *g);
int gr_gv11b_init_preemption_state(struct gk20a *g);