gpu: nvgpu: Re-generate hardware headers

JIRA NVGPU-218

Change-Id: Ib00a921150612d59454d0ed76233e7e39a63d6ce
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563850
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h

@@ -344,4 +344,8 @@ static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void)
 {
 	return 0x00000005;
 }
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+	return 0x00100c10;
+}
 #endif

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h

@@ -304,6 +304,10 @@ static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
 {
 	return (r >> 0) & 0xf;
 }
+static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
+{
+	return (r >> 7) & 0x1;
+}
 static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
 {
 	return (r >> 6) & 0x1;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h

@@ -130,7 +130,7 @@ static inline u32 fuse_status_opt_fbp_r(void)
 }
 static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
 {
-	return (r >> (0 + i*0)) & 0x1;
+	return (r >> (0 + i*1)) & 0x1;
 }
 static inline u32 fuse_opt_sec_debug_en_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h

@@ -188,6 +188,14 @@ static inline u32 gmmu_pte_address_sys_w(void)
 {
 	return 0;
 }
+static inline u32 gmmu_pte_address_vid_f(u32 v)
+{
+	return (v & 0x1ffffff) << 4;
+}
+static inline u32 gmmu_pte_address_vid_w(void)
+{
+	return 0;
+}
 static inline u32 gmmu_pte_vol_w(void)
 {
 	return 1;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h

@@ -180,6 +180,10 @@ static inline u32 gr_exception_ds_m(void)
 {
 	return 0x1 << 4;
 }
+static inline u32 gr_exception_sked_m(void)
+{
+	return 0x1 << 8;
+}
 static inline u32 gr_exception1_r(void)
 {
 	return 0x00400118;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h

@@ -55,6 +55,7 @@
  */
 #ifndef _hw_trim_gp106_h_
 #define _hw_trim_gp106_h_
+
 static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(void)
 {
 	return 0x00132924;
@@ -93,7 +94,7 @@ static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(u32 r)
 }
 static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f(void)
 {
-	return 0;
+	return 0x0;
 }
 static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
 {
@@ -117,7 +118,7 @@ static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(u32 r)
 }
 static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f(void)
 {
-	return 0;
+	return 0x0;
 }
 static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
 {
@@ -141,7 +142,7 @@ static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(u32 r)
 }
 static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f(void)
 {
-	return 0;
+	return 0x0;
 }
 static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
 {
@@ -161,7 +162,7 @@ static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(void)
 }
 static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(void)
 {
-	return 0x20000000;
+	return 0x30000000;
 }
 static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(void)
 {
@@ -191,5 +192,4 @@ static inline u32 trim_sys_clk_cntr_ncsyspll_cnt_r(void)
 {
 	return 0x001373b4;
 }
-
 #endif

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h

@@ -152,6 +152,10 @@ static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
 {
 	return (r >> 8) & 0x1;
 }
+static inline u32 xve_cya_2_r(void)
+{
+	return 0x00000704;
+}
 static inline u32 xve_reset_r(void)
 {
 	return 0x00000718;
@@ -200,9 +204,4 @@ static inline u32 xve_reset_clock_counter_val_v(u32 r)
 {
 	return (r >> 17) & 0x7ff;
 }
-static inline u32 xve_cya_2_r(void)
-{
-	return 0x00000704;
-}
-
 #endif