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gpu: nvgpu: mm: code complexity cleanup mm.c

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This patch divides complex code segments into smaller functions to
reduce code complexity in mm.c.

Jira NVGPU-4065

Change-Id: I06d45ace3609bbda8513d9fad20cff20c5f0604a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204233
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-09-25 16:53:42 -07:00
committed by Alex Waterman
parent 9f8470d37c
commit dad25b79f1
1 changed files with 65 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

104
drivers/gpu/nvgpu/common/mm/mm.c
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@@ -403,6 +403,69 @@ clean_up_va:
return err;
}
static int nvgpu_init_mm_setup_bar(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
int err;
err = nvgpu_init_bar1_vm(mm);
if (err != 0) {
return err;
}
if (g->ops.mm.init_bar2_vm != NULL) {
err = g->ops.mm.init_bar2_vm(g);
if (err != 0) {
return err;
}
}
err = nvgpu_init_system_vm(mm);
if (err != 0) {
return err;
}
err = nvgpu_init_hwpm(mm);
if (err != 0) {
return err;
}
return err;
}
static int nvgpu_init_mm_setup_vm(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
int err;
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_VM)) {
err = nvgpu_init_engine_ucode_vm(g, &mm->sec2, "sec2");
if (err != 0) {
return err;
}
}
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_GSP_VM)) {
err = nvgpu_init_engine_ucode_vm(g, &mm->gsp, "gsp");
if (err != 0) {
return err;
}
}
if (g->has_cde) {
err = nvgpu_init_cde_vm(mm);
if (err != 0) {
return err;
}
}
err = nvgpu_init_ce_vm(mm);
if (err != 0) {
return err;
}
return err;
}
static int nvgpu_init_mm_setup_sw(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
@@ -453,49 +516,12 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g)
return err;
}
err = nvgpu_init_bar1_vm(mm);
err = nvgpu_init_mm_setup_bar(g);
if (err != 0) {
return err;
}
if (g->ops.mm.init_bar2_vm != NULL) {
err = g->ops.mm.init_bar2_vm(g);
if (err != 0) {
return err;
}
}
err = nvgpu_init_system_vm(mm);
if (err != 0) {
return err;
}
err = nvgpu_init_hwpm(mm);
if (err != 0) {
return err;
}
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_VM)) {
err = nvgpu_init_engine_ucode_vm(g, &mm->sec2, "sec2");
if (err != 0) {
return err;
}
}
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_GSP_VM)) {
err = nvgpu_init_engine_ucode_vm(g, &mm->gsp, "gsp");
if (err != 0) {
return err;
}
}
if (g->has_cde) {
err = nvgpu_init_cde_vm(mm);
if (err != 0) {
return err;
}
}
err = nvgpu_init_ce_vm(mm);
err = nvgpu_init_mm_setup_vm(g);
if (err != 0) {
return err;
}