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gpu: nvgpu: Disable GR functional intrs on safety

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Disable below interrupts on safety as they do not report any error
condition and are not used by CUDA and Graphics(VKSC) on safety
build.
Signoff from CUDA and VKSC is on Bug https://nvbugs/3588603

1. NV_PGRAPH_INTR_NOTIFY: This intr is set when the Notification
     style is WRITE_THEN_AWAKEN.
2. NV_PGRAPH_INTR_SEMAPHORE: This is set when a 3d class sempahore is
     released as the result ofa SetSemaphoreD method, when the
     AwakenEnable field is TRUE.
3. NV_PGRAPH_INTR_BUFFER_NOTIFY: This bit is set when a Mem2mem DMA
     completes and the LaunchDma method specifies the interrupt type
     as INTERRUPT
4. NV_PGRAPH_INTR_DEBUG_METHODS: This is debug feature and not used
     on QNX safety

Bug 3588603
JIRA NVGPU-8166

Change-Id: I6d07dfd2857ac047fac4599421600d364251df76
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2694363
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2022-04-08 05:44:30 +00:00
committed by mobile promotions
parent 83fe3fd35e
commit dae284c74b
5 changed files with 63 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c
View File

@@ -38,23 +38,25 @@
#include <nvgpu/hw/ga100/hw_gr_ga100.h>
#define GR_INTR_EN_MASK (\
gr_intr_en_notify__prod_f() | \
gr_intr_en_semaphore__prod_f() | \
gr_intr_en_illegal_method__prod_f() | \
gr_intr_en_illegal_class__prod_f() | \
gr_intr_en_illegal_notify__prod_f() | \
gr_intr_en_debug_method__prod_f() | \
gr_intr_en_firmware_method__prod_f() | \
gr_intr_en_buffer_notify__prod_f() | \
gr_intr_en_fecs_error__prod_f() | \
gr_intr_en_class_error__prod_f() | \
gr_intr_en_exception__prod_f() | \
gr_intr_en_fe_debug_intr__prod_f())
u32 ga100_gr_intr_enable_mask(struct gk20a *g)
{
return GR_INTR_EN_MASK;
u32 mask =
#ifdef CONFIG_NVGPU_NON_FUSA
gr_intr_en_notify__prod_f() |
gr_intr_en_semaphore__prod_f() |
gr_intr_en_buffer_notify__prod_f() |
gr_intr_en_debug_method__prod_f() |
#endif
gr_intr_en_illegal_method__prod_f() |
gr_intr_en_illegal_class__prod_f() |
gr_intr_en_illegal_notify__prod_f() |
gr_intr_en_firmware_method__prod_f() |
gr_intr_en_fecs_error__prod_f() |
gr_intr_en_class_error__prod_f() |
gr_intr_en_exception__prod_f() |
gr_intr_en_fe_debug_intr__prod_f();
return mask;
}
u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g,
@@ -64,6 +66,7 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g,
(void) memset(intr_info, 0, sizeof(struct nvgpu_gr_intr_info));
#ifdef CONFIG_NVGPU_NON_FUSA
if ((gr_intr & gr_intr_notify_pending_f()) != 0U) {
intr_info->notify = gr_intr_notify_pending_f();
}
@@ -72,6 +75,14 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g,
intr_info->semaphore = gr_intr_semaphore_pending_f();
}
if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) {
intr_info->buffer_notify = gr_intr_buffer_notify_pending_f();
}
if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) {
intr_info->debug_method = gr_intr_debug_method_pending_f();
}
#endif
if ((gr_intr & gr_intr_illegal_notify_pending_f()) != 0U) {
intr_info->illegal_notify = gr_intr_illegal_notify_pending_f();
}
@@ -84,10 +95,6 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g,
intr_info->illegal_class = gr_intr_illegal_class_pending_f();
}
if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) {
intr_info->buffer_notify = gr_intr_buffer_notify_pending_f();
}
if ((gr_intr & gr_intr_fecs_error_pending_f()) != 0U) {
intr_info->fecs_error = gr_intr_fecs_error_pending_f();
}
@@ -96,10 +103,6 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g,
intr_info->class_error = gr_intr_class_error_pending_f();
}
if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) {
intr_info->debug_method = gr_intr_debug_method_pending_f();
}
/* this one happens if someone tries to hit a non-whitelisted
* register using set_falcon[4] */
if ((gr_intr & gr_intr_firmware_method_pending_f()) != 0U) {

27
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
View File

@@ -43,13 +43,16 @@
static u32 gr_intr_en_mask(void)
{
u32 mask = gr_intr_en_notify__prod_f() |
u32 mask =
#ifdef CONFIG_NVGPU_NON_FUSA
gr_intr_en_notify__prod_f() |
gr_intr_en_semaphore__prod_f() |
gr_intr_en_debug_method__prod_f() |
gr_intr_en_buffer_notify__prod_f() |
#endif
gr_intr_en_illegal_method__prod_f() |
gr_intr_en_illegal_notify__prod_f() |
gr_intr_en_debug_method__prod_f() |
gr_intr_en_firmware_method__prod_f() |
gr_intr_en_buffer_notify__prod_f() |
gr_intr_en_fecs_error__prod_f() |
gr_intr_en_class_error__prod_f() |
gr_intr_en_exception__prod_f() |
@@ -1112,6 +1115,7 @@ u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g,
(void) memset(intr_info, 0, sizeof(struct nvgpu_gr_intr_info));
#ifdef CONFIG_NVGPU_NON_FUSA
if ((gr_intr & gr_intr_notify_pending_f()) != 0U) {
intr_info->notify = gr_intr_notify_pending_f();
}
@@ -1120,6 +1124,15 @@ u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g,
intr_info->semaphore = gr_intr_semaphore_pending_f();
}
if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) {
intr_info->buffer_notify = gr_intr_buffer_notify_pending_f();
}
if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) {
intr_info->debug_method = gr_intr_debug_method_pending_f();
}
#endif
if ((gr_intr & gr_intr_illegal_notify_pending_f()) != 0U) {
intr_info->illegal_notify = gr_intr_illegal_notify_pending_f();
}
@@ -1128,10 +1141,6 @@ u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g,
intr_info->illegal_method = gr_intr_illegal_method_pending_f();
}
if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) {
intr_info->buffer_notify = gr_intr_buffer_notify_pending_f();
}
if ((gr_intr & gr_intr_fecs_error_pending_f()) != 0U) {
intr_info->fecs_error = gr_intr_fecs_error_pending_f();
}
@@ -1140,10 +1149,6 @@ u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g,
intr_info->class_error = gr_intr_class_error_pending_f();
}
if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) {
intr_info->debug_method = gr_intr_debug_method_pending_f();
}
/* this one happens if someone tries to hit a non-whitelisted
* register using set_falcon[4] */
if ((gr_intr & gr_intr_firmware_method_pending_f()) != 0U) {

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c
View File

@@ -54,6 +54,7 @@ u32 gm20b_gr_intr_read_pending_interrupts(struct gk20a *g,
(void) memset(intr_info, 0, sizeof(struct nvgpu_gr_intr_info));
#ifdef CONFIG_NVGPU_NON_FUSA
if ((gr_intr & gr_intr_notify_pending_f()) != 0U) {
intr_info->notify = gr_intr_notify_pending_f();
}
@@ -61,6 +62,7 @@ u32 gm20b_gr_intr_read_pending_interrupts(struct gk20a *g,
if ((gr_intr & gr_intr_semaphore_pending_f()) != 0U) {
intr_info->semaphore = gr_intr_semaphore_pending_f();
}
#endif
if ((gr_intr & gr_intr_illegal_notify_pending_f()) != 0U) {
intr_info->illegal_notify = gr_intr_illegal_notify_pending_f();