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gpu: nvgpu: move mc_intr_pbus from stall (intr_0) to nonstall (intr_1) tree

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Nvgpu does not support nested interrupts and as a result priv/pbus
interrupt do not reach cpu while other interrupts on intr_0 (stall)
tree are being processed. This issue is not specific to priv/pbus
but since pbus errors are critical, it is important to detect it
early on.

Below is the snippet from one of the failing logs where nvgpu
is doing recovery to process gr interrupt.
Right after GR engine is reset (PGRAPH of PMC_ENABLE), failing priv
accesses should have triggered pbus interrupt but it does not reach cpu
until gr interrupt is handled. Any interrupt that requires recovery will
take longer to finish isr as recovery is done as part of isr.
Also intr_0 (stall) interrupts are paused while stall interrupt is being
processed.

gm20b_gr_falcon_bind_instblk:147  [ERR]  arbiter idle timeout, status: badf1020
gm20b_gr_falcon_wait_for_fecs_arb_idle:125  [ERR]  arbiter idle timeout, fecs ctxsw status: 0xbadf1020

Fix to detect pbus intr while other stall interrupts are being processed
is to move pbus intr enable/disable/clear/handle to nonstall (intr_1)
tree. Configure pbus_intr_en_1 to route pbus to nostall tree.
Priv interrupts cannot be moved to nonstall (intr_1) tree due
to h/w not supporting this.

In Turing, moving pbus intr to nonstall is not feasible as mc_intr(1)
tree is deprecated. Add Turing specific stall intr handler hals with
original logic to route pbus intr to mc_intr(0).

JIRA NVGPU-25
Bug 200603566

Change-Id: I36fc376800802f20a0ea581b4f787bcc6c73ec7e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2354192
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Seema Khowala
2020-06-01 16:00:56 -07:00
committed by Alex Waterman
parent 58c7969687
commit db30ea3362
17 changed files with 137 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
userspace/units/bus/nvgpu-bus.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -125,8 +125,8 @@ int test_bus_setup(struct unit_module *m, struct gk20a *g, void *args)
g->ops.bus.bar1_bind = gm20b_bus_bar1_bind;
g->ops.bus.bar2_bind = gp10b_bus_bar2_bind;
g->ops.bus.configure_debug_bus = gv11b_bus_configure_debug_bus;
g->ops.mc.intr_stall_unit_config =
mc_gp10b_intr_stall_unit_config;
g->ops.mc.intr_nonstall_unit_config =
mc_gp10b_intr_nonstall_unit_config;
g->ops.ptimer.isr = gk20a_ptimer_isr;
/* Map register space NV_PRIV_MASTER */
@@ -181,7 +181,7 @@ int test_init_hw(struct unit_module *m, struct gk20a *g, void *args)
p->is_silicon = false;
g->ops.bus.configure_debug_bus = NULL;
ret = g->ops.bus.init_hw(g);
assert(nvgpu_readl(g, bus_intr_en_0_r()) == 0U);
assert(nvgpu_readl(g, bus_intr_en_1_r()) == 0U);
assert(nvgpu_readl(g, bus_debug_sel_0_r()) == 0xFU);
assert(nvgpu_readl(g, bus_debug_sel_1_r()) == 0xFU);
assert(nvgpu_readl(g, bus_debug_sel_2_r()) == 0xFU);
@@ -190,7 +190,7 @@ int test_init_hw(struct unit_module *m, struct gk20a *g, void *args)
p->is_silicon = true;
g->ops.bus.configure_debug_bus = gv11b_bus_configure_debug_bus;
ret = g->ops.bus.init_hw(g);
assert(nvgpu_readl(g, bus_intr_en_0_r()) == 0xEU);
assert(nvgpu_readl(g, bus_intr_en_1_r()) == 0xEU);
assert(nvgpu_readl(g, bus_debug_sel_0_r()) == 0x0U);
assert(nvgpu_readl(g, bus_debug_sel_1_r()) == 0x0U);
assert(nvgpu_readl(g, bus_debug_sel_2_r()) == 0x0U);
@@ -199,7 +199,7 @@ int test_init_hw(struct unit_module *m, struct gk20a *g, void *args)
p->is_fpga = true;
p->is_silicon = false;
ret = g->ops.bus.init_hw(g);
assert(nvgpu_readl(g, bus_intr_en_0_r()) == 0xEU);
assert(nvgpu_readl(g, bus_intr_en_1_r()) == 0xEU);
ret = UNIT_SUCCESS;
done:
return ret;

7
userspace/units/mc/nvgpu-mc.c
View File

@@ -492,7 +492,10 @@ int test_isr_stall(struct unit_module *m, struct gk20a *g, void *args)
nvgpu_posix_io_writel_reg_space(g, mc_intr_ltc_r(), 1U);
reset_ctx();
g->ops.mc.isr_stall(g);
if (!u.bus_isr || !u.ce_isr || !u.fb_isr || !u.fifo_isr || !u.gr_isr ||
if (u.bus_isr) {
unit_return_fail(m, "BUS ISR called from Stall\n");
}
if (!u.ce_isr || !u.fb_isr || !u.fifo_isr || !u.gr_isr ||
!u.pmu_isr || !u.priv_ring_isr) {
unit_return_fail(m, "not all ISRs called\n");
}
@@ -599,7 +602,7 @@ int test_isr_nonstall(struct unit_module *m, struct gk20a *g, void *args)
u.fifo_isr_return = 0x2;
u.gr_isr_return = 0x4;
val = g->ops.mc.isr_nonstall(g);
if (!u.ce_isr || !u.fifo_isr || !u.gr_isr) {
if (!u.bus_isr || !u.ce_isr || !u.fifo_isr || !u.gr_isr) {
unit_return_fail(m, "not all ISRs called\n");
}
if (val != 0x7) {