nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: fix MISRA Rule 16.x violations in pmu

Browse Source 
MISRA Rule 16.4 emphasizes on having a non-empty default label
for every switch case

MISRA Rule 16.6 emphasizes that every switch statement
shall have atleast two switch-clauses

JIRA NVGPU-1545
JIRA NVGPU-1557

Change-Id: I2d124ac0d66d8c490c59d262ddc647045d455633
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970216
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2018-12-11 14:20:35 +05:30
committed by mobile promotions
parent 7a4c2f050f
commit db533523c0
3 changed files with 15 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/lpwr/rppg.c
View File

@@ -39,11 +39,13 @@ static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x",
msg->msg.pg.msg_type);
break;
default:
*success = 0;
nvgpu_err(g, "Invalid message ID:%u",
msg->msg.pg.rppg_msg.cmn.msg_id);
break;
}
}
nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x",
msg->msg.pg.msg_type);
}
static int rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
@@ -120,9 +122,14 @@ static int rppg_ctrl_init(struct gk20a *g, u8 ctrl_id)
switch (ctrl_id) {
case NV_PMU_RPPG_CTRL_ID_GR:
rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX;
break;
case NV_PMU_RPPG_CTRL_ID_MS:
rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX;
break;
default:
nvgpu_err(g, "Invalid ctrl_id %u for %s", ctrl_id, __func__);
break;
}
return rppg_send_cmd(g, &rppg_cmd);