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gpu: nvgpu: add CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag

Browse Source 
Following are removed for safety build by adding
CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag.

1) HAL ops in g->ops.sync.syncpt

add_wait_cmd
get_wait_cmd_size
add_incr_cmd
get_incr_cmd_size
get_incr_per_release

2) g->ops.sync.sema is removed in its entirety and contains the
following ops.

3) The following files are compiled out using the above flag.
hal/sync/sema_cmdbuf_gk20a.c
hal/sync/sema_cmdbuf_gv11b.c

Jira NVGPU-3479

Change-Id: I99ae6913e5fe5707ff9a3e2cf06cee8710def7cc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2019-06-04 16:44:31 +05:30
committed by mobile promotions
parent f6c96f620f
commit db80498307
13 changed files with 54 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -245,8 +245,6 @@ srcs += common/utils/enabled.c \
hal/netlist/netlist_gm20b.c \
hal/netlist/netlist_gp10b.c \
hal/netlist/netlist_gv11b.c \
hal/sync/sema_cmdbuf_gk20a.c \
hal/sync/sema_cmdbuf_gv11b.c \
hal/sync/syncpt_cmdbuf_gk20a.c \
hal/sync/syncpt_cmdbuf_gv11b.c \
hal/pmu/pmu_gp106.c \
@@ -332,7 +330,9 @@ endif
ifeq ($(CONFIG_NVGPU_KERNEL_MODE_SUBMIT),1)
srcs += common/fifo/submit.c \
common/sync/channel_sync_semaphore.c \
hal/fifo/userd_gv11b.c
hal/fifo/userd_gv11b.c \
hal/sync/sema_cmdbuf_gk20a.c \
hal/sync/sema_cmdbuf_gv11b.c
endif
ifeq ($(CONFIG_NVGPU_FECS_TRACE),1)

6
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -486,6 +486,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.syncpt = {
.alloc_buf = gk20a_syncpt_alloc_buf,
.free_buf = gk20a_syncpt_free_buf,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.add_wait_cmd = gk20a_syncpt_add_wait_cmd,
.get_wait_cmd_size =
gk20a_syncpt_get_wait_cmd_size,
@@ -494,14 +495,17 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.add_incr_cmd = gk20a_syncpt_add_incr_cmd,
.get_incr_cmd_size =
gk20a_syncpt_get_incr_cmd_size,
#endif
.get_sync_ro_map = NULL,
},
#endif
#endif /* CONFIG_TEGRA_GK20A_NVHOST */
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.sema = {
.get_wait_cmd_size = gk20a_sema_get_wait_cmd_size,
.get_incr_cmd_size = gk20a_sema_get_incr_cmd_size,
.add_cmd = gk20a_sema_add_cmd,
},
#endif
},
.engine_status = {
.read_engine_status_info = NULL,

4
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -573,6 +573,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.syncpt = {
.alloc_buf = vgpu_gv11b_syncpt_alloc_buf,
.free_buf = vgpu_gv11b_syncpt_free_buf,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.add_wait_cmd = gv11b_syncpt_add_wait_cmd,
.get_wait_cmd_size =
gv11b_syncpt_get_wait_cmd_size,
@@ -581,14 +582,17 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.add_incr_cmd = gv11b_syncpt_add_incr_cmd,
.get_incr_cmd_size =
gv11b_syncpt_get_incr_cmd_size,
#endif
.get_sync_ro_map = vgpu_gv11b_syncpt_get_sync_ro_map,
},
#endif
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.sema = {
.get_wait_cmd_size = gv11b_sema_get_wait_cmd_size,
.get_incr_cmd_size = gv11b_sema_get_incr_cmd_size,
.add_cmd = gv11b_sema_add_cmd,
},
#endif
},
.engine_status = {
.read_engine_status_info = NULL,

6
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -670,6 +670,7 @@ static const struct gpu_ops gm20b_ops = {
.syncpt = {
.alloc_buf = gk20a_syncpt_alloc_buf,
.free_buf = gk20a_syncpt_free_buf,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.add_wait_cmd = gk20a_syncpt_add_wait_cmd,
.get_incr_per_release =
gk20a_syncpt_get_incr_per_release,
@@ -678,14 +679,17 @@ static const struct gpu_ops gm20b_ops = {
.add_incr_cmd = gk20a_syncpt_add_incr_cmd,
.get_incr_cmd_size =
gk20a_syncpt_get_incr_cmd_size,
#endif
.get_sync_ro_map = NULL,
},
#endif
#endif /* CONFIG_TEGRA_GK20A_NVHOST */
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.sema = {
.get_wait_cmd_size = gk20a_sema_get_wait_cmd_size,
.get_incr_cmd_size = gk20a_sema_get_incr_cmd_size,
.add_cmd = gk20a_sema_add_cmd,
},
#endif
},
.engine_status = {
.read_engine_status_info =

6
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -751,6 +751,7 @@ static const struct gpu_ops gp10b_ops = {
.syncpt = {
.alloc_buf = gk20a_syncpt_alloc_buf,
.free_buf = gk20a_syncpt_free_buf,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.add_wait_cmd = gk20a_syncpt_add_wait_cmd,
.get_incr_per_release =
gk20a_syncpt_get_incr_per_release,
@@ -759,14 +760,17 @@ static const struct gpu_ops gp10b_ops = {
.add_incr_cmd = gk20a_syncpt_add_incr_cmd,
.get_incr_cmd_size =
gk20a_syncpt_get_incr_cmd_size,
#endif
.get_sync_ro_map = NULL,
},
#endif
#endif /* CONFIG_TEGRA_GK20A_NVHOST */
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.sema = {
.get_wait_cmd_size = gk20a_sema_get_wait_cmd_size,
.get_incr_cmd_size = gk20a_sema_get_incr_cmd_size,
.add_cmd = gk20a_sema_add_cmd,
},
#endif
},
.engine_status = {
.read_engine_status_info =

6
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -884,6 +884,7 @@ static const struct gpu_ops gv11b_ops = {
.syncpt = {
.alloc_buf = gv11b_syncpt_alloc_buf,
.free_buf = gv11b_syncpt_free_buf,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.add_wait_cmd = gv11b_syncpt_add_wait_cmd,
.get_wait_cmd_size =
gv11b_syncpt_get_wait_cmd_size,
@@ -892,14 +893,17 @@ static const struct gpu_ops gv11b_ops = {
gv11b_syncpt_get_incr_cmd_size,
.get_incr_per_release =
gv11b_syncpt_get_incr_per_release,
#endif
.get_sync_ro_map = gv11b_syncpt_get_sync_ro_map,
},
#endif
#endif /* CONFIG_TEGRA_GK20A_NVHOST */
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.sema = {
.get_wait_cmd_size = gv11b_sema_get_wait_cmd_size,
.get_incr_cmd_size = gv11b_sema_get_incr_cmd_size,
.add_cmd = gv11b_sema_add_cmd,
},
#endif
},
.engine_status = {
.read_engine_status_info =

6
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -929,6 +929,7 @@ static const struct gpu_ops tu104_ops = {
.syncpt = {
.alloc_buf = gv11b_syncpt_alloc_buf,
.free_buf = gv11b_syncpt_free_buf,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.add_wait_cmd = gv11b_syncpt_add_wait_cmd,
.get_wait_cmd_size =
gv11b_syncpt_get_wait_cmd_size,
@@ -937,14 +938,17 @@ static const struct gpu_ops tu104_ops = {
gv11b_syncpt_get_incr_cmd_size,
.get_incr_per_release =
gv11b_syncpt_get_incr_per_release,
#endif
.get_sync_ro_map = gv11b_syncpt_get_sync_ro_map,
},
#endif
#endif /* CONFIG_TEGRA_GK20A_NVHOST */
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.sema = {
.get_wait_cmd_size = gv11b_sema_get_wait_cmd_size,
.get_incr_cmd_size = gv11b_sema_get_incr_cmd_size,
.add_cmd = gv11b_sema_add_cmd,
},
#endif
},
.engine_status = {
.read_engine_status_info =

2
drivers/gpu/nvgpu/hal/sync/syncpt_cmdbuf_gk20a.c
View File

@@ -28,6 +28,7 @@
#include "syncpt_cmdbuf_gk20a.h"
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va)
@@ -91,6 +92,7 @@ u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd)
return 6U;
}
}
#endif
void gk20a_syncpt_free_buf(struct nvgpu_channel *c,
struct nvgpu_mem *syncpt_buf)

5
drivers/gpu/nvgpu/hal/sync/syncpt_cmdbuf_gk20a.h
View File

@@ -30,6 +30,7 @@ struct nvgpu_mem;
#ifdef CONFIG_TEGRA_GK20A_NVHOST
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va);
@@ -39,6 +40,8 @@ void gk20a_syncpt_add_incr_cmd(struct gk20a *g,
bool wfi_cmd, struct priv_cmd_entry *cmd,
u32 id, u64 gpu_va);
u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd);
#endif
void gk20a_syncpt_free_buf(struct nvgpu_channel *c,
struct nvgpu_mem *syncpt_buf);
@@ -47,6 +50,7 @@ int gk20a_syncpt_alloc_buf(struct nvgpu_channel *c,
#else
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
static inline void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va)
@@ -69,6 +73,7 @@ static inline u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd)
{
return 0U;
}
#endif
static inline void gk20a_syncpt_free_buf(struct nvgpu_channel *c,
struct nvgpu_mem *syncpt_buf)
{

2
drivers/gpu/nvgpu/hal/sync/syncpt_cmdbuf_gv11b.c
View File

@@ -116,6 +116,7 @@ int gv11b_syncpt_get_sync_ro_map(struct vm_gk20a *vm,
return 0;
}
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
void gv11b_syncpt_add_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va_base)
@@ -192,3 +193,4 @@ u32 gv11b_syncpt_get_incr_cmd_size(bool wfi_cmd)
{
return 10U;
}
#endif

6
drivers/gpu/nvgpu/hal/sync/syncpt_cmdbuf_gv11b.h
View File

@@ -32,6 +32,7 @@ struct vm_gk20a;
#ifdef CONFIG_TEGRA_GK20A_NVHOST
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
void gv11b_syncpt_add_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va);
@@ -41,6 +42,8 @@ void gv11b_syncpt_add_incr_cmd(struct gk20a *g,
bool wfi_cmd, struct priv_cmd_entry *cmd,
u32 id, u64 gpu_va);
u32 gv11b_syncpt_get_incr_cmd_size(bool wfi_cmd);
#endif /* CONFIG_NVGPU_KERNEL_MODE_SUBMIT */
void gv11b_syncpt_free_buf(struct nvgpu_channel *c,
struct nvgpu_mem *syncpt_buf);
@@ -52,6 +55,7 @@ int gv11b_syncpt_get_sync_ro_map(struct vm_gk20a *vm,
#else
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
static inline void gv11b_syncpt_add_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va)
@@ -74,6 +78,8 @@ static inline u32 gv11b_syncpt_get_incr_cmd_size(bool wfi_cmd)
{
return 0U;
}
#endif
static inline void gv11b_syncpt_free_buf(struct nvgpu_channel *c,
struct nvgpu_mem *syncpt_buf)
{

1
drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h
View File

@@ -35,6 +35,7 @@
struct nvgpu_channel;
struct nvgpu_channel_sync_syncpt;
struct priv_cmd_entry;
#ifdef CONFIG_TEGRA_GK20A_NVHOST

8
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1191,6 +1191,7 @@ struct gpu_ops {
struct nvgpu_mem *syncpt_buf);
void (*free_buf)(struct nvgpu_channel *c,
struct nvgpu_mem *syncpt_buf);
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
void (*add_wait_cmd)(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va);
@@ -1200,11 +1201,13 @@ struct gpu_ops {
struct priv_cmd_entry *cmd,
u32 id, u64 gpu_va);
u32 (*get_incr_cmd_size)(bool wfi_cmd);
u32 (*get_incr_per_release)(void);
#endif
int (*get_sync_ro_map)(struct vm_gk20a *vm,
u64 *base_gpuva, u32 *sync_size);
u32 (*get_incr_per_release)(void);
} syncpt;
#endif
#endif /* CONFIG_TEGRA_GK20A_NVHOST */
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
struct {
u32 (*get_wait_cmd_size)(void);
u32 (*get_incr_cmd_size)(void);
@@ -1213,6 +1216,7 @@ struct gpu_ops {
struct priv_cmd_entry *cmd,
u32 off, bool acquire, bool wfi);
} sema;
#endif
} sync;
struct {
int (*alloc_inst)(struct gk20a *g, struct nvgpu_channel *ch);