nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 11:04:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: HAL-ify pmm type broadcast values

Browse Source 
The PMM type-specific broadcast->unicast expansion calculation
was using incorrect values.  This caused the invalid register
accesses to be generated.

This change HAL-ifies the values, so that the expansion will be
performed correctly.

Bug 200454109

Change-Id: I96c15de27b5e16e4db2e788fd98e6bf7d6e7d564
Signed-off-by: Matthew Braun <matthewb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921717
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
matthewb
2018-10-04 13:34:47 -05:00
committed by mobile promotions
parent 12acc96687
commit db8324ff98
5 changed files with 61 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -243,6 +243,27 @@ static u32 gv100_get_litter_value(struct gk20a *g, int value)
case GPU_LIT_GPC_PRIV_STRIDE:
ret = proj_gpc_priv_stride_v();
break;
case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
ret = 2;
break;
case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
ret = 9;
break;
case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
ret = 7;
break;
case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
ret = 2;
break;
case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
ret = 4;
break;
case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
ret = 6;
break;
case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
ret = 2;
break;
default:
nvgpu_err(g, "Missing definition %d", value);
BUG();

21
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -4920,14 +4920,17 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
u32 offset = 0;
if (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA) {
pmm_domain_start = NV_PERF_PMMGPCTPCA_DOMAIN_START;
num_domains = NV_PERF_PMMGPC_NUM_DOMAINS;
pmm_domain_start = nvgpu_get_litter_value(g,
GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START);
num_domains = nvgpu_get_litter_value(g,
GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT);
offset = PRI_PMMGS_OFFSET_MASK(addr);
} else if (broadcast_flags &
PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB) {
pmm_domain_start = NV_PERF_PMMGPCTPCA_DOMAIN_START +
NV_PERF_PMMGPC_NUM_DOMAINS;
num_domains = NV_PERF_PMMGPC_NUM_DOMAINS;
pmm_domain_start = nvgpu_get_litter_value(g,
GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START);
num_domains = nvgpu_get_litter_value(g,
GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT);
offset = PRI_PMMGS_OFFSET_MASK(addr);
} else if (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_GPCS) {
pmm_domain_start = (addr -
@@ -4969,15 +4972,15 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
gr_gv11b_split_pmm_fbp_broadcast_address(g,
PRI_PMMGS_OFFSET_MASK(addr),
priv_addr_table, &t,
NV_PERF_PMMFBP_LTC_DOMAIN_START,
NV_PERF_PMMFBP_LTC_NUM_DOMAINS);
nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START),
nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT));
} else if ((addr_type == CTXSW_ADDR_TYPE_ROP) &&
(broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP)) {
gr_gv11b_split_pmm_fbp_broadcast_address(g,
PRI_PMMGS_OFFSET_MASK(addr),
priv_addr_table, &t,
NV_PERF_PMMFBP_ROP_DOMAIN_START,
NV_PERF_PMMFBP_ROP_NUM_DOMAINS);
nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START),
nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT));
} else if ((addr_type == CTXSW_ADDR_TYPE_FBP) &&
(broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPS)) {
u32 domain_start;

7
drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h
View File

@@ -37,13 +37,6 @@
#define NV_PERF_PMMGPC_GPCS 0x00278000
#define NV_PERF_PMMFBP_FBPS 0x0027C000
#define NV_PERF_PMMGPCTPCA_DOMAIN_START 2
#define NV_PERF_PMMFBP_LTC_DOMAIN_START 2
#define NV_PERF_PMMFBP_ROP_DOMAIN_START 6
#define NV_PERF_PMMGPC_NUM_DOMAINS 7
#define NV_PERF_PMMFBP_LTC_NUM_DOMAINS 4
#define NV_PERF_PMMFBP_ROP_NUM_DOMAINS 2
#define PRI_PMMGS_ADDR_WIDTH 9
#define PRI_PMMS_ADDR_WIDTH 14

21
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -223,6 +223,27 @@ u32 gv11b_get_litter_value(struct gk20a *g, int value)
case GPU_LIT_GPC_PRIV_STRIDE:
ret = proj_gpc_priv_stride_v();
break;
case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
ret = 2;
break;
case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
ret = 6;
break;
case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
ret = 4;
break;
case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
ret = 1;
break;
case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
ret = 2;
break;
case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
ret = 3;
break;
case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
ret = 2;
break;
default:
nvgpu_err(g, "Missing definition %d", value);
BUG();

7
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -136,6 +136,13 @@ enum gk20a_cbc_op {
#define GPU_LIT_I2M_CLASS 35
#define GPU_LIT_DMA_COPY_CLASS 36
#define GPU_LIT_GPC_PRIV_STRIDE 37
#define GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START 38
#define GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START 39
#define GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT 40
#define GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START 41
#define GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT 42
#define GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START 43
#define GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT 44
#define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)