gpu: nvgpu: unit: add gr_config tests

Add support for the fuse and gv11b_gr related
registers and with initialized values need for
gr_config tests.

Add unit tests covering following functions
nvgpu_gr_alloc
nvgpu_gr_config_init
nvgpu_gr_config_deinit
nvgpu_gr_free

Most of the gr_config.h get and set functions
will be used in config_check_set_get test

Jira NVGPU-3582

Change-Id: I69637b3047d844559ac5b44ffd366551af8ea12c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2176369
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/libnvgpu-drv_safe.export

@@ -59,6 +59,39 @@ nvgpu_bar1_writel
 nvgpu_bitmap_clear
 nvgpu_bitmap_set
 nvgpu_bsearch
+nvgpu_gr_alloc
+nvgpu_gr_free
+nvgpu_gr_config_init
+nvgpu_gr_config_deinit
+nvgpu_gr_config_get_max_gpc_count
+nvgpu_gr_config_get_max_tpc_count
+nvgpu_gr_config_get_max_tpc_per_gpc_count
+nvgpu_gr_config_get_gpc_count
+nvgpu_gr_config_get_tpc_count
+nvgpu_gr_config_get_ppc_count
+nvgpu_gr_config_get_pe_count_per_gpc
+nvgpu_gr_config_get_sm_count_per_tpc
+nvgpu_gr_config_get_gpc_mask
+nvgpu_gr_config_get_gpc_ppc_count
+nvgpu_gr_config_get_gpc_skip_mask
+nvgpu_gr_config_get_gpc_tpc_count
+nvgpu_gr_config_get_pes_tpc_count
+nvgpu_gr_config_get_pes_tpc_mask
+nvgpu_gr_config_get_gpc_tpc_mask_base
+nvgpu_gr_config_get_gpc_tpc_count_base
+nvgpu_gr_config_set_no_of_sm
+nvgpu_gr_config_get_no_of_sm
+nvgpu_gr_config_get_sm_info
+nvgpu_gr_config_set_sm_info_gpc_index
+nvgpu_gr_config_get_sm_info_gpc_index
+nvgpu_gr_config_set_sm_info_tpc_index
+nvgpu_gr_config_get_sm_info_tpc_index
+nvgpu_gr_config_set_sm_info_global_tpc_index
+nvgpu_gr_config_get_sm_info_global_tpc_index
+nvgpu_gr_config_set_sm_info_sm_index
+nvgpu_gr_config_get_sm_info_sm_index
+nvgpu_gr_config_set_gpc_tpc_mask
+nvgpu_gr_config_get_gpc_tpc_mask
 nvgpu_channel_alloc_inst
 nvgpu_channel_cleanup_sw
 nvgpu_channel_close

userspace/Makefile.sources

@@ -70,6 +70,8 @@ UNITS :=				\
 	$(UNIT_SRC)/fifo/tsg		\
 	$(UNIT_SRC)/list		\
 	$(UNIT_SRC)/enabled		\
+	$(UNIT_SRC)/gr			\
+	$(UNIT_SRC)/gr/config		\
 	$(UNIT_SRC)/falcon		\
 	$(UNIT_SRC)/falcon/falcon_tests		\
 	$(UNIT_SRC)/pmu

userspace/units/gr/Makefile

@@ -0,0 +1,27 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = nvgpu-gr.o nvgpu-gr-gv11b.o
+
+MODULE = nvgpu-gr
+
+include ../Makefile.units

userspace/units/gr/Makefile.interface.tmk

@@ -0,0 +1,29 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All Rights Reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+# tmake for SW Mobile component makefile
+#
+# libnvgpu-gr interface makefile fragment
+#
+###############################################################################
+
+ifdef NV_INTERFACE_FLAG_SHARED_LIBRARY_SECTION
+
+NV_INTERFACE_NAME            := nvgpu-gr
+NV_INTERFACE_EXPORTS         := lib$(NV_INTERFACE_NAME)
+NV_INTERFACE_SONAME          := lib$(NV_INTERFACE_NAME).so
+
+endif
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/gr/Makefile.tmk

@@ -0,0 +1,26 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019 NVIDIA CORPORATION.  All Rights Reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+# tmake for SW Mobile component makefile
+#
+# Component makefile for compiling nvgpu-fifo common tests.
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = nvgpu-gr
+NVGPU_UNIT_SRCS = nvgpu-gr.c nvgpu-gr-gv11b.c
+
+include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/gr/config/Makefile

@@ -0,0 +1,33 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = nvgpu-gr-config.o
+MODULE = nvgpu-gr-config
+
+LIB_PATHS += -lnvgpu-gr
+include ../../Makefile.units
+
+lib$(MODULE).so: nvgpu-gr
+
+nvgpu-gr:
+	$(MAKE) -C ..
+

userspace/units/gr/config/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=nvgpu-gr-config
+
+include $(NV_COMPONENT_DIR)/../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/gr/config/Makefile.tmk

@@ -0,0 +1,40 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = nvgpu-gr-config
+NVGPU_UNIT_SRCS = nvgpu-gr-config.c
+
+NVGPU_UNIT_INTERFACE_DIRS := \
+	$(NV_COMPONENT_DIR)/.. \
+	$(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu
+
+include $(NV_COMPONENT_DIR)/../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/gr/config/nvgpu-gr-config.c

@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#include <stdlib.h>
+
+#include <unit/unit.h>
+#include <unit/io.h>
+
+#include <nvgpu/posix/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gr/config.h>
+
+#include "common/gr/gr_config_priv.h"
+
+#include "../nvgpu-gr.h"
+
+static struct nvgpu_gr_config *unit_gr_config;
+
+static int test_gr_config_init(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	unit_gr_config = nvgpu_gr_config_init(g);
+	if (unit_gr_config == NULL) {
+		return UNIT_FAIL;
+	}
+
+	return UNIT_SUCCESS;
+}
+
+static int test_gr_config_deinit(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	if (unit_gr_config != NULL) {
+		nvgpu_gr_config_deinit(g, unit_gr_config);
+		return UNIT_SUCCESS;
+	}
+
+	return UNIT_FAIL;
+}
+
+static int test_gr_config_count(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	u32 val = 0U;
+	u32 *reg_base = NULL;
+	u32 gindex = 0U, pindex = 0U;
+	u32 pes_tpc_val = 0U;
+	u32 pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC] = {0x2, 0x2, 0x0};
+	u32 pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC] = {0x5, 0xa, 0x0};
+	u32 gpc_tpc_mask = 0xf;
+	u32 gpc_skip_mask = 0x0;
+	u32 gpc_tpc_count = 0x4;
+	u32 gpc_ppc_count = 0x2;
+
+	struct nvgpu_gr_config gv11b_gr_config = {
+		.g = NULL,
+		.max_gpc_count = 0x1,
+		.max_tpc_per_gpc_count = 0x4,
+		.max_tpc_count = 0x4,
+		.gpc_count = 0x1,
+		.tpc_count = 0x4,
+		.ppc_count = 0x2,
+		.pe_count_per_gpc = 0x2,
+		.sm_count_per_tpc = 0x2,
+		.gpc_ppc_count = &gpc_ppc_count,
+		.gpc_tpc_count = &gpc_tpc_count,
+		.pes_tpc_count = {NULL, NULL, NULL},
+		.gpc_mask = 0x1,
+		.gpc_tpc_mask = &gpc_tpc_mask,
+		.pes_tpc_mask = {NULL, NULL, NULL},
+		.gpc_skip_mask = &gpc_skip_mask,
+		.no_of_sm = 0x0,
+		.sm_to_cluster = NULL,
+	};
+
+	gv11b_gr_config.pes_tpc_mask[0] = &pes_tpc_mask[0];
+	gv11b_gr_config.pes_tpc_mask[1] = &pes_tpc_mask[1];
+	gv11b_gr_config.pes_tpc_count[0] = &pes_tpc_count[0];
+	gv11b_gr_config.pes_tpc_count[1] = &pes_tpc_count[1];
+
+	/*
+	 * Compare the config registers value against
+	 * gv11b silicon following poweron
+	 */
+
+	val = nvgpu_gr_config_get_max_gpc_count(unit_gr_config);
+	if (val != gv11b_gr_config.max_gpc_count) {
+		unit_err(m, " mismatch in max_gpc_count\n");
+		goto init_fail;
+	}
+
+	val = nvgpu_gr_config_get_max_tpc_count(unit_gr_config);
+	if (val != gv11b_gr_config.max_tpc_count) {
+		unit_err(m, " mismatch in max_tpc_count\n");
+		goto init_fail;
+	}
+
+	val = nvgpu_gr_config_get_max_tpc_per_gpc_count(unit_gr_config);
+	if (val != gv11b_gr_config.max_tpc_per_gpc_count) {
+		unit_err(m, " mismatch in max_tpc_per_gpc_count\n");
+		goto init_fail;
+	}
+
+	val = nvgpu_gr_config_get_gpc_count(unit_gr_config);
+	if (val != gv11b_gr_config.gpc_count) {
+		unit_err(m, " mismatch in gpc_count\n");
+		goto init_fail;
+	}
+
+	val = nvgpu_gr_config_get_tpc_count(unit_gr_config);
+	if (val != gv11b_gr_config.tpc_count) {
+		unit_err(m, " mismatch in tpc_count\n");
+		goto init_fail;
+	}
+
+	val = nvgpu_gr_config_get_ppc_count(unit_gr_config);
+	if (val != gv11b_gr_config.ppc_count) {
+		unit_err(m, " mismatch in ppc_count\n");
+		goto init_fail;
+	}
+
+	val = nvgpu_gr_config_get_pe_count_per_gpc(unit_gr_config);
+	if (val != gv11b_gr_config.pe_count_per_gpc) {
+		unit_err(m, " mismatch in pe_count_per_gpc\n");
+		goto init_fail;
+	}
+
+	val = nvgpu_gr_config_get_sm_count_per_tpc(unit_gr_config);
+	if (val != gv11b_gr_config.sm_count_per_tpc) {
+		unit_err(m, " mismatch in sm_count_per_tpc\n");
+		goto init_fail;
+	}
+
+	val = nvgpu_gr_config_get_gpc_mask(unit_gr_config);
+	if (val != gv11b_gr_config.gpc_mask) {
+		unit_err(m, " mismatch in gpc_mask\n");
+		goto init_fail;
+	}
+
+	for (gindex = 0U; gindex < gv11b_gr_config.gpc_count;
+							gindex++) {
+		val = nvgpu_gr_config_get_gpc_ppc_count(unit_gr_config,
+							gindex);
+		if (val != gv11b_gr_config.gpc_ppc_count[gindex]) {
+			unit_err(m, " mismatch in gpc_ppc_count\n");
+			goto init_fail;
+		}
+
+		val = nvgpu_gr_config_get_gpc_skip_mask(unit_gr_config,
+							gindex);
+		if (val != gv11b_gr_config.gpc_skip_mask[gindex]) {
+			unit_err(m, " mismatch in gpc_skip_mask\n");
+			goto init_fail;
+		}
+
+		val = nvgpu_gr_config_get_gpc_tpc_count(unit_gr_config,
+							gindex);
+		if (val != gv11b_gr_config.gpc_tpc_count[gindex]) {
+			unit_err(m, " mismatch in gpc_tpc_count\n");
+			goto init_fail;
+		}
+
+		for (pindex = 0U; pindex < gv11b_gr_config.gpc_count;
+							pindex++) {
+			pes_tpc_val =
+				gv11b_gr_config.pes_tpc_count[pindex][gindex];
+			val = nvgpu_gr_config_get_pes_tpc_count(
+					unit_gr_config, gindex, pindex);
+			if (val != pes_tpc_val) {
+				unit_err(m, " mismatch in pes_tpc_count\n");
+				goto init_fail;
+			}
+
+			pes_tpc_val =
+				gv11b_gr_config.pes_tpc_mask[pindex][gindex];
+			val = nvgpu_gr_config_get_pes_tpc_mask(
+					unit_gr_config, gindex, pindex);
+			if (val != pes_tpc_val) {
+				unit_err(m, " mismatch in pes_tpc_count\n");
+				goto init_fail;
+			}
+		}
+	}
+
+	/*
+	 * Check for valid memory
+	 */
+	reg_base = nvgpu_gr_config_get_gpc_tpc_mask_base(unit_gr_config);
+	if (reg_base == NULL) {
+		unit_err(m, " Invalid gpc_tpc_mask_base\n");
+		goto init_fail;
+	}
+
+	reg_base = nvgpu_gr_config_get_gpc_tpc_count_base(unit_gr_config);
+	if (reg_base == NULL) {
+		unit_err(m, " Invalid gpc_tpc_count_base\n");
+		goto init_fail;
+	}
+
+	return UNIT_SUCCESS;
+
+init_fail:
+	return UNIT_FAIL;
+}
+
+static int test_gr_config_set_get(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	u32 gindex = 0U;
+	u32 val = 0U;
+	struct nvgpu_sm_info *sm_info;
+
+	srand(0);
+
+	/*
+	 * Set random value and read back
+	 */
+	val = (u32)rand();
+	nvgpu_gr_config_set_no_of_sm(unit_gr_config, val);
+	if (val != nvgpu_gr_config_get_no_of_sm(unit_gr_config)) {
+		unit_err(m, " mismatch in no_of_sm\n");
+		goto set_get_fail;
+	}
+
+	sm_info = nvgpu_gr_config_get_sm_info(unit_gr_config, 0);
+	val = (u32)rand();
+	nvgpu_gr_config_set_sm_info_gpc_index(sm_info, val);
+	if (val != nvgpu_gr_config_get_sm_info_gpc_index(sm_info)) {
+		unit_err(m, " mismatch in sm_info_gindex\n");
+		goto set_get_fail;
+	}
+
+	val = (u32)rand();
+	nvgpu_gr_config_set_sm_info_tpc_index(sm_info, val);
+	if (val != nvgpu_gr_config_get_sm_info_tpc_index(sm_info)) {
+		unit_err(m, " mismatch in sm_info_tpc_index\n");
+		goto set_get_fail;
+	}
+
+	val = (u32)rand();
+	nvgpu_gr_config_set_sm_info_global_tpc_index(sm_info, val);
+	if (val !=
+		nvgpu_gr_config_get_sm_info_global_tpc_index(sm_info)) {
+		unit_err(m, " mismatch in sm_info_global_tpc_index\n");
+		goto set_get_fail;
+	}
+
+	val = (u32)rand();
+	nvgpu_gr_config_set_sm_info_sm_index(sm_info, val);
+	if (val != nvgpu_gr_config_get_sm_info_sm_index(sm_info)) {
+		unit_err(m, " mismatch in sm_info_sm_index\n");
+		goto set_get_fail;
+	}
+
+	for (gindex = 0U; gindex < unit_gr_config->gpc_count;
+							gindex++) {
+		val = (u32)rand();
+		nvgpu_gr_config_set_gpc_tpc_mask(unit_gr_config, gindex, val);
+		if (val !=
+		    nvgpu_gr_config_get_gpc_tpc_mask(unit_gr_config, gindex)) {
+			unit_err(m, " mismatch in gpc_tpc_mask\n");
+			goto set_get_fail;
+		}
+	}
+
+	return UNIT_SUCCESS;
+
+set_get_fail:
+	return UNIT_FAIL;
+}
+
+struct unit_module_test nvgpu_gr_config_tests[] = {
+	UNIT_TEST(init_support, test_gr_init_support, NULL, 0),
+	UNIT_TEST(config_init, test_gr_config_init, NULL, 0),
+	UNIT_TEST(config_check_init, test_gr_config_count, NULL, 0),
+	UNIT_TEST(config_check_set_get, test_gr_config_set_get, NULL, 0),
+	UNIT_TEST(config_deinit, test_gr_config_deinit, NULL, 0),
+	UNIT_TEST(remove_support, test_gr_remove_support, NULL, 0),
+};
+
+UNIT_MODULE(nvgpu_gr_config, nvgpu_gr_config_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/gr/libnvgpu-gr.export

@@ -0,0 +1,25 @@
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+
+test_gr_init_support
+test_gr_remove_support
+

userspace/units/gr/nvgpu-gr-gv11b.c

@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/posix/io.h>
+#include <nvgpu/posix/soc_fuse.h>
+
+#include <nvgpu/gk20a.h>
+
+#include "hal/fuse/fuse_gm20b.h"
+
+#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
+
+#include "nvgpu-gr-gv11b.h"
+#include "nvgpu-gr-gv11b-regs.h"
+
+/*
+ * Mock I/O
+ */
+
+/*
+ * Write callback. Forward the write access to the mock IO framework.
+ */
+static void writel_access_reg_fn(struct gk20a *g,
+		struct nvgpu_reg_access *access)
+{
+	nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
+}
+
+/*
+ * Read callback. Get the register value from the mock IO framework.
+ */
+static void readl_access_reg_fn(struct gk20a *g,
+		struct nvgpu_reg_access *access)
+{
+	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
+}
+
+static int tegra_fuse_readl_access_reg_fn(unsigned long offset, u32 *value)
+{
+	if (offset == FUSE_GCPLEX_CONFIG_FUSE_0) {
+		*value = GCPLEX_CONFIG_WPR_ENABLED_MASK;
+	}
+	return 0;
+}
+
+static struct nvgpu_posix_io_callbacks gr_test_reg_callbacks = {
+	/* Write APIs all can use the same accessor. */
+	.writel          = writel_access_reg_fn,
+	.writel_check    = writel_access_reg_fn,
+	.bar1_writel     = writel_access_reg_fn,
+	.usermode_writel = writel_access_reg_fn,
+
+	/* Likewise for the read APIs. */
+	.__readl         = readl_access_reg_fn,
+	.readl           = readl_access_reg_fn,
+	.bar1_readl      = readl_access_reg_fn,
+
+	.tegra_fuse_readl = tegra_fuse_readl_access_reg_fn,
+};
+
+int test_gr_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
+{
+	/* Create register space */
+	nvgpu_posix_io_init_reg_space(g);
+
+	if (nvgpu_posix_io_register_reg_space(g,
+			&gv11b_master_reg_space) != 0) {
+		unit_err(m, "%s: failed to create master register space\n",
+				__func__);
+		return UNIT_FAIL;
+	}
+
+	if (nvgpu_posix_io_register_reg_space(g, &gv11b_top_reg_space) != 0) {
+		unit_err(m, "%s: failed to create top register space\n",
+				__func__);
+		goto clean_up_master;
+	}
+
+	if (nvgpu_posix_io_register_reg_space(g, &gv11b_fuse_reg_space) != 0) {
+		unit_err(m, "%s: failed to create fuse register space\n",
+				__func__);
+		goto clean_up_top;
+	}
+
+	if (nvgpu_posix_io_register_reg_space(g, &gv11b_gr_reg_space) != 0) {
+		unit_err(m, "%s: failed to create gr register space\n",
+				__func__);
+		goto clean_up_fuse;
+	}
+
+	if (nvgpu_posix_io_register_reg_space(g, &gv11b_priv_ring_reg_space) != 0) {
+		unit_err(m, "%s: failed to create priv_ring register space\n",
+				__func__);
+		goto clean_up_gr;
+	}
+
+	if (nvgpu_posix_io_register_reg_space(g, &gv11b_gr_pes_tpc_mask_reg_space) != 0) {
+		unit_err(m, "%s: failed to create gr pes_tpc_mask register space\n",
+				__func__);
+		goto clean_up_priv_ring;
+	}
+
+	if (nvgpu_posix_io_register_reg_space(g, &gv11b_gr_fs_reg_space) != 0) {
+		unit_err(m, "%s: failed to create gr floorsweep register space\n",
+				__func__);
+		goto clean_up_pes_tpc_mask;
+	}
+
+	/*
+	 * MC register mc_enable_r() is set during gr_init_prepare_hw hence
+	 * add it to reg space
+	 */
+	if (nvgpu_posix_io_add_reg_space(g,
+					 mc_enable_r(), 0x4) != 0) {
+		unit_err(m, "Add mc enable reg space failed!\n");
+		goto clean_up_priv_ring;
+	}
+
+	(void)nvgpu_posix_register_io(g, &gr_test_reg_callbacks);
+
+	return 0;
+
+clean_up_pes_tpc_mask:
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_pes_tpc_mask_reg_space);
+clean_up_priv_ring:
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_priv_ring_reg_space);
+clean_up_gr:
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_reg_space);
+clean_up_fuse:
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_fuse_reg_space);
+clean_up_top:
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_top_reg_space);
+clean_up_master:
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_master_reg_space);
+	return -ENOMEM;
+}
+
+
+void test_gr_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
+{
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_top_reg_space);
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_master_reg_space);
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_fuse_reg_space);
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_reg_space);
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_priv_ring_reg_space);
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_pes_tpc_mask_reg_space);
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_fs_reg_space);
+}

userspace/units/gr/nvgpu-gr-gv11b.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_NVGPU_GR_GV11B_H
+#define UNIT_NVGPU_GR_GV11b_H
+
+int test_gr_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g);
+void test_gr_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g);
+
+#endif /* UNIT_NVGPU_GR_GV11B_H */

userspace/units/gr/nvgpu-gr.c

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#include <stdlib.h>
+
+#include <unit/unit.h>
+#include <unit/io.h>
+
+#include <nvgpu/posix/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gr/gr.h>
+
+#include "hal/init/hal_gv11b.h"
+
+#include "nvgpu-gr.h"
+#include "nvgpu-gr-gv11b.h"
+
+int test_gr_init_support(struct unit_module *m, struct gk20a *g, void *args)
+{
+	int err;
+
+	err = test_gr_setup_gv11b_reg_space(m, g);
+	if (err != 0) {
+		goto fail;
+	}
+
+	gv11b_init_hal(g);
+
+	/*
+	 * Allocate gr unit
+	 */
+	err = nvgpu_gr_alloc(g);
+	if (err != 0) {
+		unit_err(m, " Gr allocation failed!\n");
+		return -ENOMEM;
+	}
+
+	return UNIT_SUCCESS;
+
+fail:
+	return UNIT_FAIL;
+}
+
+int test_gr_remove_support(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	nvgpu_gr_free(g);
+
+	return UNIT_SUCCESS;
+}

userspace/units/gr/nvgpu-gr.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef UNIT_NVGPU_GR_H
+#define UNIT_NVGPU_GR_H
+
+#include <nvgpu/types.h>
+
+#ifdef UNIT_GR_DEBUG
+#define unit_verbose	unit_info
+#else
+#define unit_verbose(unit, msg, ...) \
+	do { \
+		if (0) \
+			{ unit_info(unit, msg, ##__VA_ARGS__); \
+		} \
+	} while (0)
+#endif
+
+int test_gr_init_support(struct unit_module *m,
+		struct gk20a *g, void *args);
+int test_gr_remove_support(struct unit_module *m,
+		struct gk20a *g, void *args);
+
+#endif /* UNIT_NVGPU_GR_H */