gpu: nvgpu: Add gr_priv header file

Move nvgpu_gr structure to private file gr_priv.h
Include the private file where gr variables are used.

JIRA NVGPU-3132
JIRA NVGPU-3079

Change-Id: Ib26ca5c5cb25fd8dd013a7c643278efc34aa55d4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098021
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c

@@ -27,6 +27,7 @@
 #include <nvgpu/string.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/gr/gr_falcon.h>
+#include "common/gr/gr_priv.h"
 
 #include "acr_blob_construct_v0.h"
 #include "acr_falcon_bl.h"

drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c

@@ -26,6 +26,7 @@
 #include <nvgpu/string.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/gr/gr_falcon.h>
+#include "common/gr/gr_priv.h"
 
 #include "acr_blob_construct_v1.h"
 #include "acr_falcon_bl.h"

drivers/gpu/nvgpu/common/ecc.c

@@ -25,6 +25,8 @@
 #include <nvgpu/ltc.h>
 #include <nvgpu/nvgpu_err.h>
 
+#include "common/gr/gr_priv.h"
+
 static void nvgpu_ecc_stat_add(struct gk20a *g, struct nvgpu_ecc_stat *stat)
 {
 	struct nvgpu_ecc *ecc = &g->ecc;

drivers/gpu/nvgpu/common/fifo/channel.c

@@ -52,6 +52,7 @@
 #include <nvgpu/fifo/userd.h>
 #include <nvgpu/fence.h>
 
+#include "common/gr/gr_priv.h"
 #include "gk20a/gr_gk20a.h"
 
 static void free_channel(struct fifo_gk20a *f, struct channel_gk20a *ch);

drivers/gpu/nvgpu/common/fifo/tsg.c

@@ -34,6 +34,8 @@
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/runlist.h>
 
+#include "common/gr/gr_priv.h"
+
 #include "gk20a/gr_gk20a.h"
 
 void nvgpu_tsg_disable(struct tsg_gk20a *tsg)

drivers/gpu/nvgpu/common/gr/fecs_trace.c

@@ -33,6 +33,8 @@
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/fecs_trace.h>
 
+#include "common/gr/gr_priv.h"
+
 #ifdef CONFIG_GK20A_CTXSW_TRACE
 
 static int nvgpu_gr_fecs_trace_periodic_polling(void *arg);

drivers/gpu/nvgpu/common/gr/gr.c

@@ -36,6 +36,8 @@
 #include <nvgpu/gr/fecs_trace.h>
 #include <nvgpu/power_features/cg.h>
 
+#include "gr_priv.h"
+
 static int gr_alloc_global_ctx_buffers(struct gk20a *g)
 {
 	struct nvgpu_gr *gr = g->gr;

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -36,6 +36,7 @@
 #include <nvgpu/dma.h>
 
 #include "gr_falcon_priv.h"
+#include "common/gr/gr_priv.h"
 
 #define NVGPU_FECS_UCODE_IMAGE	"fecs.bin"
 #define NVGPU_GPCCS_UCODE_IMAGE	"gpccs.bin"

drivers/gpu/nvgpu/common/gr/gr_intr.c

@@ -30,6 +30,7 @@
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/gr_intr.h>
 #include <nvgpu/gr/config.h>
+#include "common/gr/gr_priv.h"
 
 static int gr_intr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
 		bool *post_event, struct channel_gk20a *fault_ch,

drivers/gpu/nvgpu/common/gr/gr_priv.h

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_PRIV_H
+#define NVGPU_GR_PRIV_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/cond.h>
+
+struct nvgpu_gr_ctx_desc;
+struct nvgpu_gr_global_ctx_buffer_desc;
+struct nvgpu_gr_obj_ctx_golden_image;
+struct nvgpu_gr_config;
+struct nvgpu_gr_zbc;
+struct nvgpu_gr_hwpm_map;
+struct nvgpu_gr_zcull;
+struct gk20a_cs_snapshot;
+
+struct gr_channel_map_tlb_entry {
+	u32 curr_ctx;
+	u32 chid;
+	u32 tsgid;
+};
+
+struct nvgpu_gr {
+	struct gk20a *g;
+	struct {
+		bool golden_image_initialized;
+		u32 golden_image_size;
+
+		u32 pm_ctxsw_image_size;
+
+		u32 preempt_image_size;
+
+		u32 zcull_image_size;
+	} ctx_vars;
+
+	struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */
+
+	struct nvgpu_cond init_wq;
+	bool initialized;
+
+	u32 num_fbps;
+	u32 max_fbps_count;
+
+	struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer;
+
+	struct nvgpu_gr_obj_ctx_golden_image *golden_image;
+
+	struct nvgpu_gr_ctx_desc *gr_ctx_desc;
+
+	struct nvgpu_gr_config *config;
+
+	struct nvgpu_gr_hwpm_map *hwpm_map;
+
+	struct nvgpu_gr_zcull *zcull;
+
+	struct nvgpu_gr_zbc *zbc;
+
+	struct nvgpu_gr_falcon *falcon;
+
+#define GR_CHANNEL_MAP_TLB_SIZE		2U /* must of power of 2 */
+	struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE];
+	u32 channel_tlb_flush_index;
+	struct nvgpu_spinlock ch_tlb_lock;
+
+	void (*remove_support)(struct gk20a *g);
+	bool sw_ready;
+
+	u32 fecs_feature_override_ecc_val;
+
+	u32 cilp_preempt_pending_chid;
+
+	u32 fbp_en_mask;
+	u32 *fbp_rop_l2_en_mask;
+
+#if defined(CONFIG_GK20A_CYCLE_STATS)
+	struct nvgpu_mutex		cs_lock;
+	struct gk20a_cs_snapshot	*cs_data;
+#endif
+	u32 max_css_buffer_size;
+	u32 max_ctxsw_ring_buffer_size;
+};
+
+#endif /* NVGPU_GR_PRIV_H */
+

drivers/gpu/nvgpu/common/gr/gr_setup.c

@@ -29,6 +29,8 @@
 #include <nvgpu/gr/setup.h>
 #include <nvgpu/channel.h>
 
+#include "gr_priv.h"
+
 static int nvgpu_gr_setup_zcull(struct gk20a *g, struct channel_gk20a *c,
 				struct nvgpu_gr_ctx *gr_ctx)
 {

drivers/gpu/nvgpu/common/gr/hwpm_map.c

@@ -31,6 +31,7 @@
 
 /* needed for pri_is_ppc_addr_shared */
 #include "gk20a/gr_pri_gk20a.h"
+#include "gr_priv.h"
 
 #define NV_PCFG_BASE		0x00088000U
 #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200U
@@ -223,9 +224,10 @@ static int add_ctxsw_buffer_map_entries_subunits(
 
 static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 					struct ctxsw_buf_offset_map_entry *map,
-					u32 *count, u32 *offset, u32 max_cnt)
+					u32 *count, u32 *offset, u32 max_cnt,
+					struct nvgpu_gr_config *config)
 {
-	u32 num_gpcs = nvgpu_gr_config_get_gpc_count(g->gr->config);
+	u32 num_gpcs = nvgpu_gr_config_get_gpc_count(config);
 	u32 num_ppcs, num_tpcs, gpc_num, base;
 	u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -235,7 +237,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
 
 	for (gpc_num = 0; gpc_num < num_gpcs; gpc_num++) {
-		num_tpcs = nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc_num);
+		num_tpcs = nvgpu_gr_config_get_gpc_tpc_count(config, gpc_num);
 		base = gpc_base + (gpc_stride * gpc_num) + tpc_in_gpc_base;
 		if (add_ctxsw_buffer_map_entries_subunits(map,
 					nvgpu_netlist_get_pm_tpc_ctxsw_regs(g),
@@ -245,7 +247,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 			return -EINVAL;
 		}
 
-		num_ppcs = nvgpu_gr_config_get_gpc_ppc_count(g->gr->config, gpc_num);
+		num_ppcs = nvgpu_gr_config_get_gpc_ppc_count(config, gpc_num);
 		base = gpc_base + (gpc_stride * gpc_num) + ppc_in_gpc_base;
 		if (add_ctxsw_buffer_map_entries_subunits(map,
 					nvgpu_netlist_get_pm_ppc_ctxsw_regs(g),
@@ -368,7 +370,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
  */
 
 static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
-	struct nvgpu_gr_hwpm_map *hwpm_map)
+	struct nvgpu_gr_hwpm_map *hwpm_map, struct nvgpu_gr_config *config)
 {
 	u32 hwpm_ctxsw_buffer_size = hwpm_map->pm_ctxsw_image_size;
 	struct ctxsw_buf_offset_map_entry *map;
@@ -485,7 +487,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 
 	/* Add GPC entries */
 	if (add_ctxsw_buffer_map_entries_gpcs(g, map, &count, &offset,
-			hwpm_ctxsw_reg_count_max) != 0) {
+			hwpm_ctxsw_reg_count_max, config) != 0) {
 		goto cleanup;
 	}
 
@@ -520,7 +522,7 @@ cleanup:
  */
 int nvgpu_gr_hwmp_map_find_priv_offset(struct gk20a *g,
 	struct nvgpu_gr_hwpm_map *hwpm_map,
-	u32 addr, u32 *priv_offset)
+	u32 addr, u32 *priv_offset, struct nvgpu_gr_config *config)
 {
 	struct ctxsw_buf_offset_map_entry *map, *result, map_key;
 	int err = 0;
@@ -530,7 +532,7 @@ int nvgpu_gr_hwmp_map_find_priv_offset(struct gk20a *g,
 
 	/* Create map of pri address and pm offset if necessary */
 	if (!hwpm_map->init) {
-		err = nvgpu_gr_hwpm_map_create(g, hwpm_map);
+		err = nvgpu_gr_hwpm_map_create(g, hwpm_map, config);
 		if (err != 0) {
 			return err;
 		}

drivers/gpu/nvgpu/common/gr/obj_ctx.c

@@ -35,6 +35,7 @@
 #include <nvgpu/power_features/cg.h>
 
 #include "obj_ctx_priv.h"
+#include "gr_priv.h"
 
 void nvgpu_gr_obj_ctx_commit_inst_gpu_va(struct gk20a *g,
 	struct nvgpu_mem *inst_block, u64 gpu_va)

drivers/gpu/nvgpu/common/perf/cyclestats_snapshot.c

@@ -39,6 +39,8 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/cyclestats_snapshot.h>
 
+#include "common/gr/gr_priv.h"
+
 /* check client for pointed perfmon ownership */
 #define CONTAINS_PERFMON(cl, pm)				\
 		((cl)->perfmon_start <= (pm) &&			\

drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c

@@ -32,6 +32,8 @@
 #include <nvgpu/pmu/cmd.h>
 #include <nvgpu/dma.h>
 
+#include "common/gr/gr_priv.h"
+
 /* state transition :
  * OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
  * ON => OFF is always synchronized

drivers/gpu/nvgpu/common/rc/rc.c

@@ -32,6 +32,7 @@
 #include <nvgpu/pbdma_status.h>
 #include <nvgpu/debug.h>
 #include <nvgpu/rc.h>
+#include "common/gr/gr_priv.h"
 
 void nvgpu_rc_fifo_recover(struct gk20a *g, u32 eng_bitmask,
 			u32 hw_id, bool id_is_tsg,

drivers/gpu/nvgpu/common/regops/regops.c

@@ -23,6 +23,7 @@
  */
 
 #include "gk20a/gr_gk20a.h"
+#include "common/gr/gr_priv.h"
 
 #include <nvgpu/log.h>
 #include <nvgpu/bsearch.h>

drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c

@@ -38,6 +38,7 @@
 
 #include "ctx_vgpu.h"
 #include "common/vgpu/ivc/comm_vgpu.h"
+#include "common/gr/gr_priv.h"
 
 int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
 			struct nvgpu_gr_ctx *gr_ctx,

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c

@@ -58,6 +58,7 @@
 #include "common/gr/ctx_priv.h"
 #include "common/gr/zcull_priv.h"
 #include "common/gr/zbc_priv.h"
+#include "common/gr/gr_priv.h"
 
 static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g,
 				struct nvgpu_gr_ctx *gr_ctx,

drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.c

@@ -40,6 +40,7 @@
 #include "common/vgpu/mm/mm_vgpu.h"
 #include "common/vgpu/gr/gr_vgpu.h"
 #include "common/vgpu/ivc/comm_vgpu.h"
+#include "common/gr/gr_priv.h"
 
 u64 vgpu_connect(void)
 {

drivers/gpu/nvgpu/common/vgpu/perf/cyclestats_snapshot_vgpu.c

@@ -32,6 +32,7 @@
 
 #include "cyclestats_snapshot_vgpu.h"
 #include "common/vgpu/ivc/comm_vgpu.h"
+#include "common/gr/gr_priv.h"
 
 static struct tegra_hv_ivm_cookie *css_cookie;
 

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -64,6 +64,8 @@
 #include "gr_gk20a.h"
 #include "gr_pri_gk20a.h"
 
+#include "common/gr/gr_priv.h"
+
 #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 
@@ -870,7 +872,7 @@ int gr_gk20a_get_pm_ctx_buffer_offsets(struct gk20a *g,
 	for (i = 0; i < num_registers; i++) {
 		err = nvgpu_gr_hwmp_map_find_priv_offset(g, g->gr->hwpm_map,
 						  priv_registers[i],
-						  &priv_offset);
+						  &priv_offset, gr->config);
 		if (err != 0) {
 			nvgpu_log_fn(g, "Could not determine priv_offset for addr:0x%x",
 				      addr); /*, grPriRegStr(addr)));*/

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -25,7 +25,6 @@
 #define GR_GK20A_H
 
 #include <nvgpu/types.h>
-#include <nvgpu/cond.h>
 
 #include "mm_gk20a.h"
 
@@ -60,12 +59,6 @@ enum {
 	NVGPU_EVENT_ID_MAX = 6U,
 };
 
-struct gr_channel_map_tlb_entry {
-	u32 curr_ctx;
-	u32 chid;
-	u32 tsgid;
-};
-
 #if defined(CONFIG_GK20A_CYCLE_STATS)
 struct gk20a_cs_snapshot_client;
 struct gk20a_cs_snapshot;
@@ -79,68 +72,6 @@ struct nvgpu_preemption_modes_rec {
 	u32 default_compute_preempt_mode; /* default mode */
 };
 
-struct nvgpu_gr {
-	struct gk20a *g;
-	struct {
-		bool golden_image_initialized;
-		u32 golden_image_size;
-
-		u32 pm_ctxsw_image_size;
-
-		u32 preempt_image_size;
-
-		u32 zcull_image_size;
-	} ctx_vars;
-
-	struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */
-
-	struct nvgpu_cond init_wq;
-	bool initialized;
-
-	u32 num_fbps;
-	u32 max_fbps_count;
-
-	struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer;
-
-	struct nvgpu_gr_obj_ctx_golden_image *golden_image;
-
-	struct nvgpu_gr_ctx_desc *gr_ctx_desc;
-
-	struct nvgpu_gr_config *config;
-
-	struct nvgpu_gr_hwpm_map *hwpm_map;
-
-	struct nvgpu_gr_zcull *zcull;
-
-	struct nvgpu_gr_zbc *zbc;
-
-	struct nvgpu_gr_falcon *falcon;
-
-#define GR_CHANNEL_MAP_TLB_SIZE		2U /* must of power of 2 */
-	struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE];
-	u32 channel_tlb_flush_index;
-	struct nvgpu_spinlock ch_tlb_lock;
-
-	void (*remove_support)(struct gk20a *g);
-	bool sw_ready;
-
-	u32 fecs_feature_override_ecc_val;
-
-	u32 cilp_preempt_pending_chid;
-
-	u32 fbp_en_mask;
-	u32 *fbp_rop_l2_en_mask;
-
-#if defined(CONFIG_GK20A_CYCLE_STATS)
-	struct nvgpu_mutex			cs_lock;
-	struct gk20a_cs_snapshot	*cs_data;
-#endif
-	u32 max_css_buffer_size;
-	u32 max_ctxsw_ring_buffer_size;
-};
-
-
-
 struct nvgpu_warpstate {
 	u64 valid_warps[2];
 	u64 trapped_warps[2];

drivers/gpu/nvgpu/gm20b/gr_gm20b.c

@@ -41,6 +41,7 @@
 #include <nvgpu/engine_status.h>
 
 #include "gk20a/gr_gk20a.h"
+#include "common/gr/gr_priv.h"
 
 #include "gr_gm20b.h"
 

drivers/gpu/nvgpu/gp10b/gr_gp10b.c

@@ -48,10 +48,11 @@
 #include <nvgpu/engine_status.h>
 
 #include "gk20a/gr_gk20a.h"
-
 #include "gm20b/gr_gm20b.h"
 #include "gp10b/gr_gp10b.h"
 
+#include "common/gr/gr_priv.h"
+
 #include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
 

drivers/gpu/nvgpu/gv100/gr_gv100.c

@@ -32,6 +32,7 @@
 
 #include "gk20a/gr_gk20a.h"
 #include "gk20a/gr_pri_gk20a.h"
+#include "common/gr/gr_priv.h"
 
 #include "gv100/gr_gv100.h"
 

drivers/gpu/nvgpu/gv11b/gr_gv11b.c

@@ -49,8 +49,8 @@
 #include <nvgpu/engines.h>
 #include <nvgpu/engine_status.h>
 
-#include "gk20a/gr_gk20a.h"
 #include "gk20a/gr_pri_gk20a.h"
+#include "common/gr/gr_priv.h"
 
 #include "gm20b/gr_gm20b.h"
 

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c

@@ -29,6 +29,7 @@
 
 #include "gr_falcon_gm20b.h"
 #include "common/gr/gr_falcon_priv.h"
+#include "common/gr/gr_priv.h"
 
 #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_ram_gm20b.h>

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b.c

@@ -26,6 +26,7 @@
 #include "gr_falcon_gp10b.h"
 #include "gr_falcon_gm20b.h"
 #include "common/gr/gr_falcon_priv.h"
+#include "common/gr/gr_priv.h"
 
 #include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 

drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c

@@ -30,6 +30,8 @@
 #include <nvgpu/gr/config.h>
 #include <nvgpu/gr/gr.h>
 
+#include "common/gr/gr_priv.h"
+
 #include "gr_init_gm20b.h"
 #include "gr_init_gp10b.h"
 

drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c

@@ -30,6 +30,7 @@
 #include <nvgpu/netlist.h>
 
 #include <nvgpu/gr/config.h>
+#include "common/gr/gr_priv.h"
 
 #include "gr_init_gm20b.h"
 #include "gr_init_gv11b.h"

drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c

@@ -37,6 +37,7 @@
 #include <nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h>
 
 #include "ltc_gm20b.h"
+#include "common/gr/gr_priv.h"
 
 void gm20b_ltc_init_fs_state(struct gk20a *g)
 {

drivers/gpu/nvgpu/include/nvgpu/gr/hwpm_map.h

@@ -27,6 +27,7 @@
 
 struct gk20a;
 struct ctxsw_buf_offset_map_entry;
+struct nvgpu_gr_config;
 
 struct nvgpu_gr_hwpm_map {
 	u32 pm_ctxsw_image_size;
@@ -46,6 +47,6 @@ u32 nvgpu_gr_hwpm_map_get_size(struct nvgpu_gr_hwpm_map *hwpm_map);
 
 int nvgpu_gr_hwmp_map_find_priv_offset(struct gk20a *g,
 	struct nvgpu_gr_hwpm_map *hwpm_map,
-	u32 addr, u32 *priv_offset);
+	u32 addr, u32 *priv_offset, struct nvgpu_gr_config *config);
 
 #endif /* NVGPU_GR_HWPM_MAP_H */

drivers/gpu/nvgpu/os/linux/debug_gr.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017 NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2017-2019 NVIDIA Corporation.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -12,9 +12,11 @@
  *
  */
 
+#include <nvgpu/gk20a.h>
 #include <nvgpu/gr/ctx.h>
 
 #include "common/gr/ctx_priv.h"
+#include "common/gr/gr_priv.h"
 
 #include "debug_gr.h"
 #include "os_linux.h"

drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c

@@ -30,6 +30,7 @@
 #include <nvgpu/string.h>
 
 #include "gk20a/gr_gk20a.h"
+#include "common/gr/gr_priv.h"
 
 #include "platform_gk20a.h"
 #include "os_linux.h"

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -40,6 +40,8 @@
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/fence.h>
 
+#include "common/gr/gr_priv.h"
+
 #include "ioctl_ctrl.h"
 #include "ioctl_dbg.h"
 #include "ioctl_as.h"

drivers/gpu/nvgpu/os/linux/ioctl_dbg.c

@@ -42,6 +42,8 @@
 
 #include <nvgpu/linux/vm.h>
 
+#include "common/gr/gr_priv.h"
+
 #include "gk20a/gr_gk20a.h"
 #include "os_linux.h"
 #include "platform_gk20a.h"

drivers/gpu/nvgpu/os/linux/ioctl_tsg.c

@@ -30,6 +30,8 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/tsg.h>
 
+#include "common/gr/gr_priv.h"
+
 #include "gv11b/fifo_gv11b.h"
 #include "platform_gk20a.h"
 #include "ioctl_tsg.h"

drivers/gpu/nvgpu/os/linux/module.c

@@ -50,6 +50,8 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/gr/gr.h>
 
+#include "common/gr/gr_priv.h"
+
 #include "platform_gk20a.h"
 #include "sysfs.h"
 #include "vgpu/vgpu_linux.h"

drivers/gpu/nvgpu/os/linux/sysfs.c

@@ -29,6 +29,8 @@
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/pmu/pmu_perfmon.h>
 
+#include "common/gr/gr_priv.h"
+
 #include "os_linux.h"
 #include "sysfs.h"
 #include "platform_gk20a.h"