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gpu: nvgpu: fix pes_tpc_count

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In calculation of pes_tpc_count, accumulate the number of PEs
with TPCs connected to them instead of using the architectural
maximum number.

Bug 200250616

Change-Id: I4b2edc420ac03e24f2c298587d4dd1d77c51f5d6
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1262642
(cherry picked from commit 65723cf5be8fe24bcaf56570883f0880a198efcb)
Reviewed-on: http://git-master/r/1263958
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
This commit is contained in:
Peter Daifuku
2016-11-30 15:58:10 -08:00
committed by mobile promotions
parent 9bc735ac6a
commit dd075c39bb
1 changed files with 8 additions and 3 deletions
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11
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -3371,9 +3371,6 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
gr_gpc0_fs_gpc_num_available_zculls_v(tmp);
gr->zcb_count += gr->gpc_zcb_count[gpc_index];
gr->gpc_ppc_count[gpc_index] = gr->pe_count_per_gpc;
gr->ppc_count += gr->gpc_ppc_count[gpc_index];
if (g->ops.gr.get_gpc_tpc_mask)
gr->gpc_tpc_mask[gpc_index] =
g->ops.gr.get_gpc_tpc_mask(g, gpc_index);
@@ -3398,10 +3395,18 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
pes_tpc_mask = gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(tmp);
pes_tpc_count = count_bits(pes_tpc_mask);
/* detect PES presence by seeing if there are
* TPCs connected to it.
*/
if (pes_tpc_count != 0)
gr->gpc_ppc_count[gpc_index]++;
gr->pes_tpc_count[pes_index][gpc_index] = pes_tpc_count;
gr->pes_tpc_mask[pes_index][gpc_index] = pes_tpc_mask;
}
gr->ppc_count += gr->gpc_ppc_count[gpc_index];
gpc_new_skip_mask = 0;
if (gr->pe_count_per_gpc > 1 &&
gr->pes_tpc_count[0][gpc_index] +