gpu: nvgpu: introduce new ctxsw_addr_type LTS_MAIN

The LTS_MAIN will be used by nvgpu-next chips.

In addition, update gops_ltc.h to include nvgpu_next_gops_ltc.h and
nvgpu_next_gops_ltc_intr.h

Jira NVGPU-5352
Bug 200605474
Bug 200608785

Change-Id: Id77ddfc4c1aa2f93e98e05cfd8645f7ffb8f41c8
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2366350
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2020-06-25 00:01:41 +05:30
committed by Alex Waterman
parent 0f5818b89e
commit dd82cdca97
3 changed files with 7 additions and 2 deletions

View File

@@ -1212,7 +1212,8 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
}
if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
(addr_type == CTXSW_ADDR_TYPE_BE)) {
(addr_type == CTXSW_ADDR_TYPE_BE) ||
(addr_type == CTXSW_ADDR_TYPE_LTS_MAIN)) {
/* Find the offset in the FECS segment. */
offset_to_segment = sys_priv_offset * 256U;

View File

@@ -242,6 +242,7 @@ enum ctxsw_addr_type {
CTXSW_ADDR_TYPE_ETPC = 8,
CTXSW_ADDR_TYPE_ROP = 9,
CTXSW_ADDR_TYPE_FBP = 10,
CTXSW_ADDR_TYPE_LTS_MAIN = 11,
};
#define PRI_BROADCAST_FLAGS_NONE 0U

View File

@@ -53,7 +53,7 @@ struct gops_ltc_intr {
void (*configure)(struct gk20a *g);
void (*en_illegal_compstat)(struct gk20a *g, bool enable);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include "include/nvgpu/nvgpu_next_gops_ltc.h"
#include "include/nvgpu/nvgpu_next_gops_ltc_intr.h"
#endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
};
@@ -156,6 +156,9 @@ struct gops_ltc {
void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr,
u32 *priv_addr_table,
u32 *priv_addr_table_index);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include "include/nvgpu/nvgpu_next_gops_ltc.h"
#endif
#endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */