gpu: nvgpu: use public APIs of engine_status_info unit

nvgpu driver presently uses h/w functions to read and process
the engine_status registers. H/w headers shouldn't be directly invoked
by common code and should be called via HAL layer. This patch replaces
the h/w headers with the APIs in the engine_status_info unit.

Jira NVGPU-1315

Change-Id: I767a2b116b07cce4f4b587e6da8dd118afa27de5
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2005470
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c

@@ -24,6 +24,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/runlist.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/engine_status.h>
 
 #include <gk20a/fifo_gk20a.h>
 
@@ -50,9 +51,10 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
 		&g->fifo.runlist_info[ch->runlist_id];
 	int ret = 0;
 	u32 gr_eng_id = 0;
-	u32 engstat = 0, ctxstat = 0, fecsstat0 = 0, fecsstat1 = 0;
+	u32 fecsstat0 = 0, fecsstat1 = 0;
 	u32 preempt_id;
 	u32 preempt_type = 0;
+	struct nvgpu_engine_status_info engine_status;
 
 	if (1U != gk20a_fifo_get_engine_ids(
 		g, &gr_eng_id, 1, ENGINE_GR_GK20A)) {
@@ -68,12 +70,10 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
 	}
 
 	fecsstat0 = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0));
-	engstat = gk20a_readl(g, fifo_engine_status_r(gr_eng_id));
-	ctxstat = fifo_engine_status_ctx_status_v(engstat);
-	if (ctxstat == fifo_engine_status_ctx_status_ctxsw_switch_v()) {
-		/* host switching to next context, preempt that if needed */
-		preempt_id = fifo_engine_status_next_id_v(engstat);
-		preempt_type = fifo_engine_status_next_id_type_v(engstat);
+	g->ops.engine_status.read_engine_status_info(g, gr_eng_id, &engine_status);
+	if (nvgpu_engine_status_is_ctxsw_switch(&engine_status)) {
+		nvgpu_engine_status_get_next_ctx_id_type(&engine_status,
+			&preempt_id, &preempt_type);
 	} else {
 		return ret;
 	}
@@ -89,7 +89,8 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
 
 	gk20a_fifo_issue_preempt(g, preempt_id, preempt_type != 0U);
 #ifdef TRACEPOINTS_ENABLED
-	trace_gk20a_reschedule_preempt_next(ch->chid, fecsstat0, engstat,
+	trace_gk20a_reschedule_preempt_next(ch->chid, fecsstat0,
+		engine_status.reg_data,
 		fecsstat1, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)),
 		gk20a_readl(g, fifo_preempt_r()));
 #endif

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -52,6 +52,7 @@
 #include <nvgpu/vm_area.h>
 #include <nvgpu/top.h>
 #include <nvgpu/nvgpu_err.h>
+#include <nvgpu/engine_status.h>
 
 #include "mm_gk20a.h"
 
@@ -1308,6 +1309,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
 	unsigned long engine_mmu_fault_id;
 	bool verbose = true;
 	u32 grfifo_ctl;
+	struct nvgpu_engine_status_info engine_status;
 
 	nvgpu_log_fn(g, " ");
 
@@ -1362,15 +1364,12 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
 		struct channel_gk20a *ch = NULL;
 		struct tsg_gk20a *tsg = NULL;
 		struct channel_gk20a *refch = NULL;
+		bool ctxsw;
 		/* read and parse engine status */
-		u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id));
-		u32 ctx_status = fifo_engine_status_ctx_status_v(status);
-		bool ctxsw = (ctx_status ==
-				fifo_engine_status_ctx_status_ctxsw_switch_v()
-				|| ctx_status ==
-				fifo_engine_status_ctx_status_ctxsw_save_v()
-				|| ctx_status ==
-				fifo_engine_status_ctx_status_ctxsw_load_v());
+		g->ops.engine_status.read_engine_status_info(g, engine_id,
+			&engine_status);
+
+		ctxsw = nvgpu_engine_status_is_ctxsw(&engine_status);
 
 		get_exception_mmu_fault_info(g, (u32)engine_mmu_fault_id,
 						 &mmfault_info);
@@ -1409,24 +1408,24 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
 			u32 id, type;
 
 			if (hw_id == ~(u32)0) {
-				id = (ctx_status ==
-				      fifo_engine_status_ctx_status_ctxsw_load_v()) ?
-					fifo_engine_status_next_id_v(status) :
-					fifo_engine_status_id_v(status);
-				type = (ctx_status ==
-					fifo_engine_status_ctx_status_ctxsw_load_v()) ?
-					fifo_engine_status_next_id_type_v(status) :
-					fifo_engine_status_id_type_v(status);
+				if (nvgpu_engine_status_is_ctxsw_load(
+					&engine_status)) {
+					nvgpu_engine_status_get_next_ctx_id_type(
+						&engine_status, &id, &type);
+				} else {
+					nvgpu_engine_status_get_ctx_id_type(
+						&engine_status, &id, &type);
+				}
 			} else {
 				id = hw_id;
 				type = id_is_tsg ?
-					fifo_engine_status_id_type_tsgid_v() :
-					fifo_engine_status_id_type_chid_v();
+					ENGINE_STATUS_CTX_ID_TYPE_TSGID :
+					ENGINE_STATUS_CTX_ID_TYPE_CHID;
 			}
 
-			if (type == fifo_engine_status_id_type_tsgid_v()) {
+			if (type == ENGINE_STATUS_CTX_ID_TYPE_TSGID) {
 				tsg = &g->fifo.tsg[id];
-			} else if (type == fifo_engine_status_id_type_chid_v()) {
+			} else if (type == ENGINE_STATUS_CTX_ID_TYPE_CHID) {
 				ch = &g->fifo.channel[id];
 				refch = gk20a_channel_get(ch);
 				if (refch != NULL) {
@@ -1557,46 +1556,51 @@ static bool gk20a_fifo_handle_mmu_fault(
 static void gk20a_fifo_get_faulty_id_type(struct gk20a *g, u32 engine_id,
 					  u32 *id, u32 *type)
 {
-	u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id));
-	u32 ctx_status = fifo_engine_status_ctx_status_v(status);
+	struct nvgpu_engine_status_info engine_status;
+
+	g->ops.engine_status.read_engine_status_info(g, engine_id, &engine_status);
 
 	/* use next_id if context load is failing */
-	*id = (ctx_status ==
-		fifo_engine_status_ctx_status_ctxsw_load_v()) ?
-		fifo_engine_status_next_id_v(status) :
-		fifo_engine_status_id_v(status);
-
-	*type = (ctx_status ==
-		fifo_engine_status_ctx_status_ctxsw_load_v()) ?
-		fifo_engine_status_next_id_type_v(status) :
-		fifo_engine_status_id_type_v(status);
+	if (nvgpu_engine_status_is_ctxsw_load(
+		&engine_status)) {
+		nvgpu_engine_status_get_next_ctx_id_type(
+			&engine_status, id, type);
+	} else {
+		nvgpu_engine_status_get_ctx_id_type(
+			&engine_status, id, type);
+	}
 }
 
 u32 gk20a_fifo_engines_on_id(struct gk20a *g, u32 id, bool is_tsg)
 {
 	unsigned int i;
 	u32 engines = 0;
+	struct nvgpu_engine_status_info engine_status;
+	u32 ctx_id;
+	u32 type;
+	bool busy;
 
 	for (i = 0; i < g->fifo.num_engines; i++) {
 		u32 active_engine_id = g->fifo.active_engines_list[i];
-		u32 status = gk20a_readl(g, fifo_engine_status_r(active_engine_id));
-		u32 ctx_status =
-			fifo_engine_status_ctx_status_v(status);
-		u32 ctx_id = (ctx_status ==
-			fifo_engine_status_ctx_status_ctxsw_load_v()) ?
-			fifo_engine_status_next_id_v(status) :
-			fifo_engine_status_id_v(status);
-		u32 type = (ctx_status ==
-			fifo_engine_status_ctx_status_ctxsw_load_v()) ?
-			fifo_engine_status_next_id_type_v(status) :
-			fifo_engine_status_id_type_v(status);
-		bool busy = fifo_engine_status_engine_v(status) ==
-			fifo_engine_status_engine_busy_v();
+		g->ops.engine_status.read_engine_status_info(g,
+			active_engine_id, &engine_status);
+
+		if (nvgpu_engine_status_is_ctxsw_load(
+			&engine_status)) {
+			nvgpu_engine_status_get_next_ctx_id_type(
+				&engine_status, &ctx_id, &type);
+		} else {
+			nvgpu_engine_status_get_ctx_id_type(
+				&engine_status, &ctx_id, &type);
+		}
+
+		busy = engine_status.is_busy;
+
 		if (busy && ctx_id == id) {
 			if ((is_tsg && type ==
-					fifo_engine_status_id_type_tsgid_v()) ||
+					ENGINE_STATUS_CTX_ID_TYPE_TSGID) ||
 				    (!is_tsg && type ==
-					fifo_engine_status_id_type_chid_v())) {
+					ENGINE_STATUS_CTX_ID_TYPE_CHID)) {
 				engines |= BIT(active_engine_id);
 			}
 		}
@@ -1850,55 +1854,46 @@ u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g,
 	bool is_tsg = false;
 	u32 mailbox2;
 	u32 active_engine_id = FIFO_INVAL_ENGINE_ID;
+	struct nvgpu_engine_status_info engine_status;
 
 	for (engine_id = 0; engine_id < g->fifo.num_engines; engine_id++) {
-		u32 status;
-		u32 ctx_status;
 		bool failing_engine;
 
 		active_engine_id = g->fifo.active_engines_list[engine_id];
-		status = gk20a_readl(g, fifo_engine_status_r(active_engine_id));
-		ctx_status = fifo_engine_status_ctx_status_v(status);
+		g->ops.engine_status.read_engine_status_info(g, active_engine_id,
+			&engine_status);
 
 		/* we are interested in busy engines */
-		failing_engine = fifo_engine_status_engine_v(status) ==
-			fifo_engine_status_engine_busy_v();
+		failing_engine = engine_status.is_busy;
 
 		/* ..that are doing context switch */
 		failing_engine = failing_engine &&
-			(ctx_status ==
-				fifo_engine_status_ctx_status_ctxsw_switch_v()
-			|| ctx_status ==
-				fifo_engine_status_ctx_status_ctxsw_save_v()
-			|| ctx_status ==
-				fifo_engine_status_ctx_status_ctxsw_load_v());
+			nvgpu_engine_status_is_ctxsw(&engine_status);
 
 		if (!failing_engine) {
 		    active_engine_id = FIFO_INVAL_ENGINE_ID;
 			continue;
 		}
 
-		if (ctx_status ==
-				fifo_engine_status_ctx_status_ctxsw_load_v()) {
-			id = fifo_engine_status_next_id_v(status);
-			is_tsg = fifo_engine_status_next_id_type_v(status) !=
-				fifo_engine_status_next_id_type_chid_v();
-		} else if (ctx_status ==
-			       fifo_engine_status_ctx_status_ctxsw_switch_v()) {
+		if (nvgpu_engine_status_is_ctxsw_load(&engine_status)) {
+			id = engine_status.ctx_next_id;
+			is_tsg = nvgpu_engine_status_is_next_ctx_type_tsg(
+					&engine_status);
+		} else if (nvgpu_engine_status_is_ctxsw_switch(&engine_status)) {
 			mailbox2 = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(2));
 			if ((mailbox2 & FECS_METHOD_WFI_RESTORE) != 0U) {
-				id = fifo_engine_status_next_id_v(status);
-				is_tsg = fifo_engine_status_next_id_type_v(status) !=
-					fifo_engine_status_next_id_type_chid_v();
+				id = engine_status.ctx_next_id;
+				is_tsg = nvgpu_engine_status_is_next_ctx_type_tsg(
+						&engine_status);
 			} else {
-				id = fifo_engine_status_id_v(status);
-				is_tsg = fifo_engine_status_id_type_v(status) !=
-					fifo_engine_status_id_type_chid_v();
+				id = engine_status.ctx_id;
+				is_tsg = nvgpu_engine_status_is_ctx_type_tsg(
+						&engine_status);
 			}
 		} else {
-			id = fifo_engine_status_id_v(status);
-			is_tsg = fifo_engine_status_id_type_v(status) !=
-				fifo_engine_status_id_type_chid_v();
+			id = engine_status.ctx_id;
+			is_tsg = nvgpu_engine_status_is_ctx_type_tsg(
+					&engine_status);
 		}
 		break;
 	}
@@ -2579,20 +2574,20 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g,
 				struct fifo_engine_info_gk20a *eng_info,
 				bool wait_for_idle)
 {
-	u32 gr_stat, pbdma_stat, chan_stat, eng_stat, ctx_stat;
+	u32 pbdma_stat, chan_stat;
 	u32 pbdma_chid = FIFO_INVAL_CHANNEL_ID;
 	u32 engine_chid = FIFO_INVAL_CHANNEL_ID;
 	u32 token = PMU_INVALID_MUTEX_OWNER_ID;
 	int mutex_ret = -EINVAL;
 	struct channel_gk20a *ch = NULL;
 	int err = 0;
+	struct nvgpu_engine_status_info engine_status;
 
 	nvgpu_log_fn(g, " ");
 
-	gr_stat =
-		gk20a_readl(g, fifo_engine_status_r(eng_info->engine_id));
-	if (fifo_engine_status_engine_v(gr_stat) ==
-	    fifo_engine_status_engine_busy_v() && !wait_for_idle) {
+	g->ops.engine_status.read_engine_status_info(g, eng_info->engine_id,
+		 &engine_status);
+	if (engine_status.is_busy && !wait_for_idle) {
 		return -EBUSY;
 	}
 
@@ -2627,14 +2622,14 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g,
 	}
 
 	/* chid from engine status */
-	eng_stat = gk20a_readl(g, fifo_engine_status_r(eng_info->engine_id));
-	ctx_stat  = fifo_engine_status_ctx_status_v(eng_stat);
-	if (ctx_stat == fifo_engine_status_ctx_status_valid_v() ||
-	    ctx_stat == fifo_engine_status_ctx_status_ctxsw_save_v()) {
-		engine_chid = fifo_engine_status_id_v(eng_stat);
-	} else if (ctx_stat == fifo_engine_status_ctx_status_ctxsw_load_v() ||
-		 ctx_stat == fifo_engine_status_ctx_status_ctxsw_switch_v()) {
-		engine_chid = fifo_engine_status_next_id_v(eng_stat);
+	g->ops.engine_status.read_engine_status_info(g, eng_info->engine_id,
+		 &engine_status);
+	if (nvgpu_engine_status_is_ctxsw_valid(&engine_status) ||
+	    nvgpu_engine_status_is_ctxsw_save(&engine_status)) {
+		engine_chid = engine_status.ctx_id;
+	} else if (nvgpu_engine_status_is_ctxsw_switch(&engine_status) ||
+	    nvgpu_engine_status_is_ctxsw_load(&engine_status)) {
+		engine_chid = engine_status.ctx_next_id;
 	}
 
 	if (engine_chid != FIFO_INVAL_ENGINE_ID && engine_chid != pbdma_chid) {
@@ -2706,14 +2701,15 @@ u32 gk20a_fifo_runlist_busy_engines(struct gk20a *g, u32 runlist_id)
 	struct fifo_gk20a *f = &g->fifo;
 	u32 engines = 0;
 	unsigned int i;
+	struct nvgpu_engine_status_info engine_status;
 
 	for (i = 0; i < f->num_engines; i++) {
 		u32 active_engine_id = f->active_engines_list[i];
 		u32 engine_runlist = f->engine_info[active_engine_id].runlist_id;
-		u32 status_reg = fifo_engine_status_r(active_engine_id);
-		u32 status = gk20a_readl(g, status_reg);
-		bool engine_busy = fifo_engine_status_engine_v(status) ==
-			fifo_engine_status_engine_busy_v();
+		bool engine_busy;
+		g->ops.engine_status.read_engine_status_info(g, active_engine_id,
+			&engine_status);
+		engine_busy = engine_status.is_busy;
 
 		if (engine_busy && engine_runlist == runlist_id) {
 			engines |= BIT(active_engine_id);
@@ -2783,13 +2779,14 @@ bool gk20a_fifo_mmu_fault_pending(struct gk20a *g)
 bool gk20a_fifo_is_engine_busy(struct gk20a *g)
 {
 	u32 i, host_num_engines;
+	struct nvgpu_engine_status_info engine_status;
 
 	host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
 
 	for (i = 0; i < host_num_engines; i++) {
-		u32 status = gk20a_readl(g, fifo_engine_status_r(i));
-		if (fifo_engine_status_engine_v(status) ==
-			fifo_engine_status_engine_busy_v()) {
+		g->ops.engine_status.read_engine_status_info(g, i,
+			&engine_status);
+		if (engine_status.is_busy) {
 			return true;
 		}
 	}
@@ -2801,7 +2798,8 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g)
 	struct nvgpu_timeout timeout;
 	u32 delay = GR_IDLE_CHECK_DEFAULT;
 	int ret = 0;
-	u32 i, host_num_engines, status;
+	u32 i, host_num_engines;
+	struct nvgpu_engine_status_info engine_status;
 
 	nvgpu_log_fn(g, " ");
 
@@ -2814,9 +2812,9 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g)
 	for (i = 0; i < host_num_engines; i++) {
 		ret = -ETIMEDOUT;
 		do {
-			status = gk20a_readl(g, fifo_engine_status_r(i));
-			if (fifo_engine_status_engine_v(status) ==
-				fifo_engine_status_engine_idle_v()) {
+			g->ops.engine_status.read_engine_status_info(g, i,
+				&engine_status);
+			if (!engine_status.is_busy) {
 				ret = 0;
 				break;
 			}
@@ -2832,7 +2830,8 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g)
 			 * elcg_init_idle_filters and init_therm_setup_hw
 			 */
 			nvgpu_err(g, "cannot idle engine: %u "
-					"engine_status: 0x%08x", i, status);
+					"engine_status: 0x%08x", i,
+					engine_status.reg_data);
 			break;
 		}
 	}
@@ -3101,6 +3100,7 @@ void gk20a_dump_eng_status(struct gk20a *g,
 				 struct gk20a_debug_output *o)
 {
 	u32 i, host_num_engines;
+	struct nvgpu_engine_status_info engine_status;
 
 	host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
 
@@ -3108,27 +3108,27 @@ void gk20a_dump_eng_status(struct gk20a *g,
 	gk20a_debug_output(o, "--------------------------");
 
 	for (i = 0; i < host_num_engines; i++) {
-		u32 status = gk20a_readl(g, fifo_engine_status_r(i));
-		u32 ctx_status = fifo_engine_status_ctx_status_v(status);
+		g->ops.engine_status.read_engine_status_info(g, i, &engine_status);
 
 		gk20a_debug_output(o,
 			"Engine %d | "
 			"ID: %d - %-9s next_id: %d %-9s | status: %s",
 			i,
-			fifo_engine_status_id_v(status),
-			(fifo_engine_status_id_type_v(status) ==
-				fifo_engine_status_id_type_tsgid_v()) ?
+			engine_status.ctx_id,
+			nvgpu_engine_status_is_ctx_type_tsg(
+				&engine_status) ?
 				"[tsg]" : "[channel]",
-			fifo_engine_status_next_id_v(status),
-			(fifo_engine_status_next_id_type_v(status) ==
-				fifo_engine_status_next_id_type_tsgid_v()) ?
+			engine_status.ctx_next_id,
+			nvgpu_engine_status_is_next_ctx_type_tsg(
+				&engine_status) ?
 				"[tsg]" : "[channel]",
-			gk20a_decode_pbdma_chan_eng_ctx_status(ctx_status));
+			gk20a_decode_pbdma_chan_eng_ctx_status(
+				engine_status.ctxsw_state));
 
-		if (fifo_engine_status_faulted_v(status) != 0U) {
+		if (engine_status.is_faulted) {
 			gk20a_debug_output(o, "  State: faulted");
 		}
-		if (fifo_engine_status_engine_v(status) != 0U) {
+		if (engine_status.is_busy) {
 			gk20a_debug_output(o, "  State: busy");
 		}
 	}

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -53,6 +53,7 @@
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/engine_status.h>
 
 #include "gr_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
@@ -219,7 +220,8 @@ int gr_gk20a_wait_idle(struct gk20a *g)
 	bool ctxsw_active;
 	bool gr_busy;
 	u32 gr_engine_id;
-	u32 engine_status;
+
+	struct nvgpu_engine_status_info engine_status;
 	bool ctx_status_invalid;
 	struct nvgpu_timeout timeout;
 
@@ -235,15 +237,13 @@ int gr_gk20a_wait_idle(struct gk20a *g)
 		   only when gr_status is read */
 		(void) gk20a_readl(g, gr_status_r());
 
-		engine_status = gk20a_readl(g,
-					fifo_engine_status_r(gr_engine_id));
+		g->ops.engine_status.read_engine_status_info(g, gr_engine_id,
+			&engine_status);
 
-		ctxsw_active = (engine_status &
-			fifo_engine_status_ctxsw_in_progress_f()) != 0U;
+		ctxsw_active = engine_status.ctxsw_in_progress;
 
-		ctx_status_invalid =
-			(fifo_engine_status_ctx_status_v(engine_status) ==
-			 fifo_engine_status_ctx_status_invalid_v());
+		ctx_status_invalid = nvgpu_engine_status_is_ctxsw_invalid(
+			&engine_status);
 
 		gr_busy = (gk20a_readl(g, gr_engine_status_r()) &
 			gr_engine_status_value_busy_f()) != 0U;

drivers/gpu/nvgpu/gm20b/gr_gm20b.c

@@ -33,6 +33,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/engine_status.h>
 
 #include "gk20a/gr_gk20a.h"
 
@@ -929,6 +930,7 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
 {
 	struct gr_gk20a *gr = &g->gr;
 	u32 gr_engine_id;
+	struct nvgpu_engine_status_info engine_status;
 
 	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
 
@@ -950,8 +952,10 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
 		gk20a_readl(g, gr_exception_r()));
 	gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR  : 0x%x\n",
 		gk20a_readl(g, gr_fecs_intr_r()));
+	g->ops.engine_status.read_engine_status_info(g, gr_engine_id,
+		&engine_status);
 	gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
-		gk20a_readl(g, fifo_engine_status_r(gr_engine_id)));
+		engine_status.reg_data);
 	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
 		gk20a_readl(g, gr_activity_0_r()));
 	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -61,6 +61,7 @@
 #include "common/fifo/runlist_gk20a.h"
 #include "common/fifo/channel_gk20a.h"
 #include "common/fifo/channel_gm20b.h"
+#include "common/fifo/engine_status_gm20b.h"
 
 #include "gk20a/ce2_gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -559,6 +560,10 @@ static const struct gpu_ops gm20b_ops = {
 		.get_sema_incr_cmd_size = gk20a_get_sema_incr_cmd_size,
 		.add_sema_cmd = gk20a_add_sema_cmd,
 	},
+	.engine_status = {
+		.read_engine_status_info =
+			gm20b_read_engine_status_info,
+	},
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
 		.reload = gk20a_runlist_reload,
@@ -809,6 +814,7 @@ int gm20b_init_hal(struct gk20a *g)
 	gops->runlist = gm20b_ops.runlist;
 	gops->channel = gm20b_ops.channel;
 	gops->sync = gm20b_ops.sync;
+	gops->engine_status = gm20b_ops.engine_status;
 	gops->netlist = gm20b_ops.netlist;
 	gops->mm = gm20b_ops.mm;
 	gops->therm = gm20b_ops.therm;

drivers/gpu/nvgpu/gp10b/gr_gp10b.c

@@ -39,6 +39,7 @@
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/engine_status.h>
 
 #include "gk20a/gr_gk20a.h"
 
@@ -1186,6 +1187,7 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
 {
 	struct gr_gk20a *gr = &g->gr;
 	u32 gr_engine_id;
+	struct nvgpu_engine_status_info engine_status;
 
 	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
 
@@ -1207,8 +1209,10 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
 		gk20a_readl(g, gr_exception_r()));
 	gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR  : 0x%x\n",
 		gk20a_readl(g, gr_fecs_intr_r()));
+	g->ops.engine_status.read_engine_status_info(g, gr_engine_id,
+		&engine_status);
 	gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
-		gk20a_readl(g, fifo_engine_status_r(gr_engine_id)));
+		engine_status.reg_data);
 	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
 		gk20a_readl(g, gr_activity_0_r()));
 	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -73,6 +73,7 @@
 #include "common/fifo/runlist_gk20a.h"
 #include "common/fifo/channel_gk20a.h"
 #include "common/fifo/channel_gm20b.h"
+#include "common/fifo/engine_status_gm20b.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
@@ -610,6 +611,10 @@ static const struct gpu_ops gp10b_ops = {
 		.get_sema_incr_cmd_size = gk20a_get_sema_incr_cmd_size,
 		.add_sema_cmd = gk20a_add_sema_cmd,
 	},
+	.engine_status = {
+		.read_engine_status_info =
+			gm20b_read_engine_status_info,
+	},
 	.runlist = {
 		.reschedule_runlist = gk20a_fifo_reschedule_runlist,
 		.reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next,
@@ -892,6 +897,7 @@ int gp10b_init_hal(struct gk20a *g)
 	gops->runlist = gp10b_ops.runlist;
 	gops->channel = gp10b_ops.channel;
 	gops->sync = gp10b_ops.sync;
+	gops->engine_status = gp10b_ops.engine_status;
 	gops->netlist = gp10b_ops.netlist;
 #ifdef CONFIG_GK20A_CTXSW_TRACE
 	gops->fecs_trace = gp10b_ops.fecs_trace;

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -84,6 +84,7 @@
 #include "common/fifo/channel_gm20b.h"
 #include "common/fifo/channel_gv11b.h"
 #include "common/fifo/channel_gv100.h"
+#include "common/fifo/engine_status_gv100.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
@@ -781,6 +782,10 @@ static const struct gpu_ops gv100_ops = {
 		.get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size,
 		.add_sema_cmd = gv11b_add_sema_cmd,
 	},
+	.engine_status = {
+		.read_engine_status_info =
+			read_engine_status_info_gv100,
+	},
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
 		.reload = gk20a_runlist_reload,
@@ -1157,6 +1162,7 @@ int gv100_init_hal(struct gk20a *g)
 	gops->runlist = gv100_ops.runlist;
 	gops->channel = gv100_ops.channel;
 	gops->sync = gv100_ops.sync;
+	gops->engine_status = gv100_ops.engine_status;
 	gops->netlist = gv100_ops.netlist;
 	gops->mm = gv100_ops.mm;
 #ifdef CONFIG_GK20A_CTXSW_TRACE

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -46,6 +46,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/unit.h>
 #include <nvgpu/nvgpu_err.h>
+#include <nvgpu/engine_status.h>
 
 #include "gk20a/fifo_gk20a.h"
 
@@ -296,31 +297,34 @@ void gv11b_dump_eng_status(struct gk20a *g,
 				 struct gk20a_debug_output *o)
 {
 	u32 i, host_num_engines;
+	struct nvgpu_engine_status_info engine_status;
 
 	host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
 
 	for (i = 0; i < host_num_engines; i++) {
-		u32 status = gk20a_readl(g, fifo_engine_status_r(i));
-		u32 ctx_status = fifo_engine_status_ctx_status_v(status);
+		g->ops.engine_status.read_engine_status_info(g, i, &engine_status);
 
 		gk20a_debug_output(o, "%s eng %d: ", g->name, i);
 		gk20a_debug_output(o,
 			"id: %d (%s), next_id: %d (%s), ctx status: %s ",
-			fifo_engine_status_id_v(status),
-			(fifo_engine_status_id_type_v(status) ==
-			 fifo_engine_status_id_type_tsgid_v()) ? "tsg" : "channel",
-			fifo_engine_status_next_id_v(status),
-			(fifo_engine_status_next_id_type_v(status) ==
-			 fifo_engine_status_next_id_type_tsgid_v()) ? "tsg" : "channel",
-			gk20a_decode_pbdma_chan_eng_ctx_status(ctx_status));
+			engine_status.ctx_id,
+			nvgpu_engine_status_is_ctx_type_tsg(
+				&engine_status) ?
+				"tsg" : "channel",
+			engine_status.ctx_next_id,
+			nvgpu_engine_status_is_next_ctx_type_tsg(
+				&engine_status) ?
+				"tsg" : "channel",
+			gk20a_decode_pbdma_chan_eng_ctx_status(
+				engine_status.ctxsw_state));
 
-		if (fifo_engine_status_eng_reload_v(status) != 0U) {
+		if (engine_status.in_reload_status) {
 			gk20a_debug_output(o, "ctx_reload ");
 		}
-		if (fifo_engine_status_faulted_v(status) != 0U) {
+		if (engine_status.is_faulted) {
 			gk20a_debug_output(o, "faulted ");
 		}
-		if (fifo_engine_status_engine_v(status) != 0U) {
+		if (engine_status.is_busy) {
 			gk20a_debug_output(o, "busy ");
 		}
 		gk20a_debug_output(o, "\n");

drivers/gpu/nvgpu/gv11b/gr_gv11b.c

@@ -43,6 +43,7 @@
 #include <nvgpu/gr/config.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/nvgpu_err.h>
+#include <nvgpu/engine_status.h>
 
 #include "gk20a/gr_gk20a.h"
 #include "gk20a/gr_pri_gk20a.h"
@@ -1946,6 +1947,7 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
 {
 	struct gr_gk20a *gr = &g->gr;
 	u32 gr_engine_id;
+	struct nvgpu_engine_status_info engine_status;
 
 	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
 
@@ -1967,8 +1969,10 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
 		gk20a_readl(g, gr_exception_r()));
 	gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR  : 0x%x\n",
 		gk20a_readl(g, gr_fecs_intr_r()));
+	g->ops.engine_status.read_engine_status_info(g, gr_engine_id,
+		&engine_status);
 	gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
-		gk20a_readl(g, fifo_engine_status_r(gr_engine_id)));
+		engine_status.reg_data);
 	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
 		gk20a_readl(g, gr_activity_0_r()));
 	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -71,6 +71,7 @@
 #include "common/fifo/channel_gk20a.h"
 #include "common/fifo/channel_gm20b.h"
 #include "common/fifo/channel_gv11b.h"
+#include "common/fifo/engine_status_gv100.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
@@ -738,6 +739,10 @@ static const struct gpu_ops gv11b_ops = {
 		.get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size,
 		.add_sema_cmd = gv11b_add_sema_cmd,
 	},
+	.engine_status = {
+		.read_engine_status_info =
+			read_engine_status_info_gv100,
+	},
 	.runlist = {
 		.reschedule_runlist = gv11b_fifo_reschedule_runlist,
 		.reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next,
@@ -1028,6 +1033,7 @@ int gv11b_init_hal(struct gk20a *g)
 	gops->runlist = gv11b_ops.runlist;
 	gops->channel = gv11b_ops.channel;
 	gops->sync = gv11b_ops.sync;
+	gops->engine_status = gv11b_ops.engine_status;
 	gops->netlist = gv11b_ops.netlist;
 	gops->mm = gv11b_ops.mm;
 #ifdef CONFIG_GK20A_CTXSW_TRACE

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -89,6 +89,7 @@
 #include "common/fifo/channel_gm20b.h"
 #include "common/fifo/channel_gv11b.h"
 #include "common/fifo/channel_gv100.h"
+#include "common/fifo/engine_status_gv100.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
@@ -812,6 +813,10 @@ static const struct gpu_ops tu104_ops = {
 		.get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size,
 		.add_sema_cmd = gv11b_add_sema_cmd,
 	},
+	.engine_status = {
+		.read_engine_status_info =
+			read_engine_status_info_gv100,
+	},
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
 		.reload = gk20a_runlist_reload,
@@ -1192,6 +1197,7 @@ int tu104_init_hal(struct gk20a *g)
 	gops->runlist = tu104_ops.runlist;
 	gops->channel = tu104_ops.channel;
 	gops->sync = tu104_ops.sync;
+	gops->engine_status = tu104_ops.engine_status;
 	gops->netlist = tu104_ops.netlist;
 	gops->mm = tu104_ops.mm;
 #ifdef CONFIG_GK20A_CTXSW_TRACE

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -421,6 +421,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.get_sema_incr_cmd_size = gk20a_get_sema_incr_cmd_size,
 		.add_sema_cmd = gk20a_add_sema_cmd,
 	},
+	.engine_status = {
+		.read_engine_status_info = NULL,
+	},
 	.runlist = {
 		.reschedule_runlist = NULL,
 		.update_for_channel = vgpu_runlist_update_for_channel,
@@ -671,6 +674,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
 	gops->runlist = vgpu_gp10b_ops.runlist;
 	gops->channel = vgpu_gp10b_ops.channel;
 	gops->sync = vgpu_gp10b_ops.sync;
+	gops->engine_status = vgpu_gp10b_ops.engine_status;
 	gops->netlist = vgpu_gp10b_ops.netlist;
 #ifdef CONFIG_GK20A_CTXSW_TRACE
 	gops->fecs_trace = vgpu_gp10b_ops.fecs_trace;

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -45,6 +45,7 @@
 #include "common/regops/regops_gv11b.h"
 #include "common/fifo/runlist_gv11b.h"
 #include "common/fifo/channel_gv11b.h"
+#include "common/fifo/engine_status_gv100.h"
 
 #include <nvgpu/gk20a.h>
 #include <gv11b/hal_gv11b.h>
@@ -496,6 +497,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size,
 		.add_sema_cmd = gv11b_add_sema_cmd,
 	},
+	.engine_status = {
+		.read_engine_status_info = NULL,
+	},
 	.runlist = {
 		.reschedule_runlist = NULL,
 		.update_for_channel = vgpu_runlist_update_for_channel,
@@ -745,6 +749,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
 	gops->runlist = vgpu_gv11b_ops.runlist;
 	gops->channel = vgpu_gv11b_ops.channel;
 	gops->sync = vgpu_gv11b_ops.sync;
+	gops->engine_status = vgpu_gv11b_ops.engine_status;
 	gops->netlist = vgpu_gv11b_ops.netlist;
 	gops->mm = vgpu_gv11b_ops.mm;
 #ifdef CONFIG_GK20A_CTXSW_TRACE