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gpu: nvgpu: PMU perfmon interface header reorg
Moved perfmon interface from pmu_api.h & pmu_gk20a.h to gpmuif_perfmon.h header files gpmuif_perfmon.h - PMU Command/Message Interfaces PERFMON Jira NVGPU-19 Change-Id: I983f89f0f6ec3b889d975178fb1405f166b7d1b9 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1297262 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Mahantesh Kumbar
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@@ -17,143 +17,6 @@
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#include <nvgpu/flcnif_cmn.h>
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#include "pmuif/gpmuif_pg_rppg.h"
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/*---------------------------------------------------------*/
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/*perfmon task defines*/
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enum pmu_perfmon_cmd_start_fields {
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COUNTER_ALLOC
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};
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enum {
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PMU_PERFMON_CMD_ID_START = 0,
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PMU_PERFMON_CMD_ID_STOP = 1,
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PMU_PERFMON_CMD_ID_INIT = 2
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};
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struct pmu_perfmon_cmd_start_v3 {
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u8 cmd_type;
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u8 group_id;
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u8 state_id;
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u8 flags;
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struct pmu_allocation_v3 counter_alloc;
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};
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struct pmu_perfmon_cmd_start_v2 {
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u8 cmd_type;
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u8 group_id;
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u8 state_id;
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u8 flags;
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struct pmu_allocation_v2 counter_alloc;
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};
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struct pmu_perfmon_cmd_start_v1 {
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u8 cmd_type;
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u8 group_id;
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u8 state_id;
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u8 flags;
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struct pmu_allocation_v1 counter_alloc;
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};
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struct pmu_perfmon_cmd_start_v0 {
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u8 cmd_type;
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u8 group_id;
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u8 state_id;
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u8 flags;
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struct pmu_allocation_v0 counter_alloc;
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};
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struct pmu_perfmon_cmd_stop {
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u8 cmd_type;
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};
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struct pmu_perfmon_cmd_init_v3 {
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u8 cmd_type;
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u8 to_decrease_count;
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u8 base_counter_id;
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u32 sample_period_us;
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struct pmu_allocation_v3 counter_alloc;
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u8 num_counters;
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u8 samples_in_moving_avg;
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u16 sample_buffer;
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};
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struct pmu_perfmon_cmd_init_v2 {
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u8 cmd_type;
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u8 to_decrease_count;
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u8 base_counter_id;
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u32 sample_period_us;
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struct pmu_allocation_v2 counter_alloc;
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u8 num_counters;
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u8 samples_in_moving_avg;
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u16 sample_buffer;
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};
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struct pmu_perfmon_cmd_init_v1 {
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u8 cmd_type;
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u8 to_decrease_count;
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u8 base_counter_id;
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u32 sample_period_us;
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struct pmu_allocation_v1 counter_alloc;
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u8 num_counters;
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u8 samples_in_moving_avg;
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u16 sample_buffer;
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};
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struct pmu_perfmon_cmd_init_v0 {
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u8 cmd_type;
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u8 to_decrease_count;
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u8 base_counter_id;
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u32 sample_period_us;
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struct pmu_allocation_v0 counter_alloc;
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u8 num_counters;
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u8 samples_in_moving_avg;
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u16 sample_buffer;
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};
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struct pmu_perfmon_cmd {
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union {
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u8 cmd_type;
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struct pmu_perfmon_cmd_start_v0 start_v0;
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struct pmu_perfmon_cmd_start_v1 start_v1;
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struct pmu_perfmon_cmd_start_v2 start_v2;
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struct pmu_perfmon_cmd_start_v3 start_v3;
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struct pmu_perfmon_cmd_stop stop;
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struct pmu_perfmon_cmd_init_v0 init_v0;
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struct pmu_perfmon_cmd_init_v1 init_v1;
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struct pmu_perfmon_cmd_init_v2 init_v2;
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struct pmu_perfmon_cmd_init_v3 init_v3;
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};
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};
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struct pmu_zbc_cmd {
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u8 cmd_type;
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u8 pad;
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u16 entry_mask;
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};
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/* PERFMON MSG */
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enum {
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PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
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PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
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PMU_PERFMON_MSG_ID_INIT_EVENT = 2,
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PMU_PERFMON_MSG_ID_ACK = 3
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};
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struct pmu_perfmon_msg_generic {
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u8 msg_type;
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u8 state_id;
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u8 group_id;
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u8 data;
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};
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struct pmu_perfmon_msg {
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union {
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u8 msg_type;
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struct pmu_perfmon_msg_generic gen;
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};
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};
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/*---------------------------------------------------------*/
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/* ACR Commands/Message structures */
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enum {
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@@ -134,39 +134,6 @@ struct pmu_ucode_desc_v1 {
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*/
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#define ACR_ERROR_INVALID_TRANSCFG_SETUP (0xAC120001)
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/* PERFMON */
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#define PMU_DOMAIN_GROUP_PSTATE 0
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#define PMU_DOMAIN_GROUP_GPC2CLK 1
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#define PMU_DOMAIN_GROUP_NUM 2
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/* TBD: smart strategy */
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#define PMU_PERFMON_PCT_TO_INC 58
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#define PMU_PERFMON_PCT_TO_DEC 23
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struct pmu_perfmon_counter_v0 {
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u8 index;
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u8 flags;
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u8 group_id;
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u8 valid;
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u16 upper_threshold; /* units of 0.01% */
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u16 lower_threshold; /* units of 0.01% */
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};
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struct pmu_perfmon_counter_v2 {
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u8 index;
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u8 flags;
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u8 group_id;
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u8 valid;
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u16 upper_threshold; /* units of 0.01% */
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u16 lower_threshold; /* units of 0.01% */
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u32 scale;
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};
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#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001)
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#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002)
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#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004)
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#define PMU_PGENG_GR_BUFFER_IDX_INIT (0)
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#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1)
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#define PMU_PGENG_GR_BUFFER_IDX_FECS (2)
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178
drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h
Normal file
178
drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h
Normal file
@@ -0,0 +1,178 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _GPMUIFPERFMON_H_
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#define _GPMUIFPERFMON_H_
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/*perfmon task defines*/
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#define PMU_DOMAIN_GROUP_PSTATE 0
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#define PMU_DOMAIN_GROUP_GPC2CLK 1
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#define PMU_DOMAIN_GROUP_NUM 2
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#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001)
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#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002)
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#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004)
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enum pmu_perfmon_cmd_start_fields {
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COUNTER_ALLOC
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};
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enum {
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PMU_PERFMON_CMD_ID_START = 0,
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PMU_PERFMON_CMD_ID_STOP = 1,
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PMU_PERFMON_CMD_ID_INIT = 2
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};
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struct pmu_perfmon_counter_v0 {
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u8 index;
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u8 flags;
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u8 group_id;
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u8 valid;
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u16 upper_threshold; /* units of 0.01% */
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u16 lower_threshold; /* units of 0.01% */
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};
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struct pmu_perfmon_counter_v2 {
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u8 index;
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u8 flags;
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u8 group_id;
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u8 valid;
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u16 upper_threshold; /* units of 0.01% */
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u16 lower_threshold; /* units of 0.01% */
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u32 scale;
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};
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struct pmu_perfmon_cmd_start_v3 {
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u8 cmd_type;
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u8 group_id;
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u8 state_id;
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u8 flags;
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struct pmu_allocation_v3 counter_alloc;
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};
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struct pmu_perfmon_cmd_start_v2 {
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u8 cmd_type;
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u8 group_id;
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u8 state_id;
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u8 flags;
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struct pmu_allocation_v2 counter_alloc;
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};
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struct pmu_perfmon_cmd_start_v1 {
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u8 cmd_type;
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u8 group_id;
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u8 state_id;
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u8 flags;
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struct pmu_allocation_v1 counter_alloc;
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};
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struct pmu_perfmon_cmd_start_v0 {
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u8 cmd_type;
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u8 group_id;
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u8 state_id;
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u8 flags;
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struct pmu_allocation_v0 counter_alloc;
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};
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struct pmu_perfmon_cmd_stop {
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u8 cmd_type;
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};
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struct pmu_perfmon_cmd_init_v3 {
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u8 cmd_type;
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u8 to_decrease_count;
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u8 base_counter_id;
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u32 sample_period_us;
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struct pmu_allocation_v3 counter_alloc;
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u8 num_counters;
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u8 samples_in_moving_avg;
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u16 sample_buffer;
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};
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struct pmu_perfmon_cmd_init_v2 {
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u8 cmd_type;
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u8 to_decrease_count;
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u8 base_counter_id;
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u32 sample_period_us;
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struct pmu_allocation_v2 counter_alloc;
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u8 num_counters;
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u8 samples_in_moving_avg;
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u16 sample_buffer;
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};
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struct pmu_perfmon_cmd_init_v1 {
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u8 cmd_type;
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u8 to_decrease_count;
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u8 base_counter_id;
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u32 sample_period_us;
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struct pmu_allocation_v1 counter_alloc;
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u8 num_counters;
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u8 samples_in_moving_avg;
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u16 sample_buffer;
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};
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struct pmu_perfmon_cmd_init_v0 {
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u8 cmd_type;
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u8 to_decrease_count;
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u8 base_counter_id;
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u32 sample_period_us;
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struct pmu_allocation_v0 counter_alloc;
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u8 num_counters;
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u8 samples_in_moving_avg;
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u16 sample_buffer;
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};
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struct pmu_perfmon_cmd {
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union {
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u8 cmd_type;
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struct pmu_perfmon_cmd_start_v0 start_v0;
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struct pmu_perfmon_cmd_start_v1 start_v1;
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struct pmu_perfmon_cmd_start_v2 start_v2;
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struct pmu_perfmon_cmd_start_v3 start_v3;
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struct pmu_perfmon_cmd_stop stop;
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struct pmu_perfmon_cmd_init_v0 init_v0;
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struct pmu_perfmon_cmd_init_v1 init_v1;
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struct pmu_perfmon_cmd_init_v2 init_v2;
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struct pmu_perfmon_cmd_init_v3 init_v3;
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};
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};
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struct pmu_zbc_cmd {
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u8 cmd_type;
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u8 pad;
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u16 entry_mask;
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};
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/* PERFMON MSG */
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enum {
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PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
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PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
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PMU_PERFMON_MSG_ID_INIT_EVENT = 2,
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PMU_PERFMON_MSG_ID_ACK = 3
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};
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struct pmu_perfmon_msg_generic {
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u8 msg_type;
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u8 state_id;
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u8 group_id;
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u8 data;
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};
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struct pmu_perfmon_msg {
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union {
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u8 msg_type;
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struct pmu_perfmon_msg_generic gen;
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};
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};
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#endif /* _GPMUIFPERFMON_H_ */
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@@ -19,6 +19,7 @@
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#include "gpmuif_pmu.h"
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#include "gpmuif_ap.h"
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#include "gpmuif_pg.h"
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#include "gpmuif_perfmon.h"
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#include "gpmuifboardobj.h"
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#include "gpmuifclk.h"
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#include "gpmuifperf.h"
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