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gpu: nvgpu: gv11b: support SET_SKEDCHECK s/w methods

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Support sw method NVC397_SET_SKEDCHECK and NVC3C0_SET_SKEDCHECK
data fields are
data:0 SKEDCHECK_18_DISABLE
data:1 SKEDCHECK_18_ENABLE

Bug 200315442

Change-Id: I0652434ab0b4d6e49dab94be329072861e99c38c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515772
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Seema Khowala
2017-07-08 17:20:26 -07:00
committed by mobile promotions
parent 66fb130bfd
commit df022d27dd
2 changed files with 38 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -299,8 +299,6 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
static void gr_gv11b_enable_hww_exceptions(struct gk20a *g)
{
u32 val;
/* enable exceptions */
gk20a_writel(g, gr_fe_hww_esr_r(),
gr_fe_hww_esr_en_enable_f() |
@@ -308,14 +306,6 @@ static void gr_gv11b_enable_hww_exceptions(struct gk20a *g)
gk20a_writel(g, gr_memfmt_hww_esr_r(),
gr_memfmt_hww_esr_en_enable_f() |
gr_memfmt_hww_esr_reset_active_f());
/* WAR for 200315442 */
val = gk20a_readl(g, gr_sked_hww_esr_en_r());
val = set_field(val,
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(),
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f()
);
nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", val);
gk20a_writel(g, gr_sked_hww_esr_en_r(), val);
}
static void gr_gv11b_enable_exceptions(struct gk20a *g)
@@ -1108,6 +1098,30 @@ static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data)
gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val);
}
static void gr_gv11b_set_skedcheck(struct gk20a *g, u32 data)
{
u32 reg_val;
reg_val = gk20a_readl(g, gr_sked_hww_esr_en_r());
if ((data & NVC397_SET_SKEDCHECK_18_MASK) ==
NVC397_SET_SKEDCHECK_18_DISABLE) {
reg_val = set_field(reg_val,
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(),
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f()
);
} else if ((data & NVC397_SET_SKEDCHECK_18_MASK) ==
NVC397_SET_SKEDCHECK_18_ENABLE) {
reg_val = set_field(reg_val,
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(),
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()
);
}
nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", reg_val);
gk20a_writel(g, gr_sked_hww_esr_en_r(), reg_val);
}
static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data)
{
gk20a_dbg_fn("");
@@ -1132,6 +1146,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
case NVC0C0_SET_SHADER_EXCEPTIONS:
gv11b_gr_set_shader_exceptions(g, data);
break;
case NVC3C0_SET_SKEDCHECK:
gr_gv11b_set_skedcheck(g, data);
break;
default:
goto fail;
}
@@ -1157,6 +1174,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
case NVC397_SET_TEX_IN_DBG:
gr_gv11b_set_tex_in_dbg(g, data);
break;
case NVC397_SET_SKEDCHECK:
gr_gv11b_set_skedcheck(g, data);
break;
default:
goto fail;
}

8
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -40,11 +40,19 @@ enum {
#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c
#define NVC397_SET_TEX_IN_DBG 0x10bc
#define NVC397_SET_SKEDCHECK 0x10c0
#define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1
#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2
#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4
#define NVC397_SET_SKEDCHECK_18_MASK 0x3
#define NVC397_SET_SKEDCHECK_18_DEFAULT 0x0
#define NVC397_SET_SKEDCHECK_18_DISABLE 0x1
#define NVC397_SET_SKEDCHECK_18_ENABLE 0x2
#define NVC3C0_SET_SKEDCHECK 0x23c
#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
void gv11b_init_gr(struct gpu_ops *ops);