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gpu: nvgpu: gp10b headers

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Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/447753
This commit is contained in:
Ken Adams
2014-07-25 16:47:24 -04:00
committed by Deepak Nibade
parent 505b442551
commit dfdd5ba3cb
22 changed files with 8990 additions and 0 deletions
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105
drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_bus_gp10b_h_
#define _hw_bus_gp10b_h_
static inline u32 bus_bar1_block_r(void)
{
return 0x00001704;
}
static inline u32 bus_bar1_block_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
}
static inline u32 bus_bar1_block_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 bus_bar1_block_mode_virtual_f(void)
{
return 0x80000000;
}
static inline u32 bus_bar1_block_ptr_shift_v(void)
{
return 0x0000000c;
}
static inline u32 bus_intr_0_r(void)
{
return 0x00001100;
}
static inline u32 bus_intr_0_pri_squash_m(void)
{
return 0x1 << 1;
}
static inline u32 bus_intr_0_pri_fecserr_m(void)
{
return 0x1 << 2;
}
static inline u32 bus_intr_0_pri_timeout_m(void)
{
return 0x1 << 3;
}
static inline u32 bus_intr_en_0_r(void)
{
return 0x00001140;
}
static inline u32 bus_intr_en_0_pri_squash_m(void)
{
return 0x1 << 1;
}
static inline u32 bus_intr_en_0_pri_fecserr_m(void)
{
return 0x1 << 2;
}
static inline u32 bus_intr_en_0_pri_timeout_m(void)
{
return 0x1 << 3;
}
#endif

109
drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ccsr_gp10b_h_
#define _hw_ccsr_gp10b_h_
static inline u32 ccsr_channel_inst_r(u32 i)
{
return 0x00800000 + i*8;
}
static inline u32 ccsr_channel_inst__size_1_v(void)
{
return 0x00000200;
}
static inline u32 ccsr_channel_inst_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
}
static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 ccsr_channel_inst_bind_false_f(void)
{
return 0x0;
}
static inline u32 ccsr_channel_inst_bind_true_f(void)
{
return 0x80000000;
}
static inline u32 ccsr_channel_r(u32 i)
{
return 0x00800004 + i*8;
}
static inline u32 ccsr_channel__size_1_v(void)
{
return 0x00000200;
}
static inline u32 ccsr_channel_enable_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 ccsr_channel_enable_set_f(u32 v)
{
return (v & 0x1) << 10;
}
static inline u32 ccsr_channel_enable_set_true_f(void)
{
return 0x400;
}
static inline u32 ccsr_channel_enable_clr_true_f(void)
{
return 0x800;
}
static inline u32 ccsr_channel_status_v(u32 r)
{
return (r >> 24) & 0xf;
}
static inline u32 ccsr_channel_busy_v(u32 r)
{
return (r >> 28) & 0x1;
}
#endif

85
drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_chiplet_pwr_gp10b_h_
#define _hw_chiplet_pwr_gp10b_h_
static inline u32 chiplet_pwr_gpcs_weight_6_r(void)
{
return 0x0010e018;
}
static inline u32 chiplet_pwr_gpcs_weight_7_r(void)
{
return 0x0010e01c;
}
static inline u32 chiplet_pwr_gpcs_config_1_r(void)
{
return 0x0010e03c;
}
static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void)
{
return 0x1;
}
static inline u32 chiplet_pwr_fbps_weight_0_r(void)
{
return 0x0010e100;
}
static inline u32 chiplet_pwr_fbps_weight_1_r(void)
{
return 0x0010e104;
}
static inline u32 chiplet_pwr_fbps_config_1_r(void)
{
return 0x0010e13c;
}
static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void)
{
return 0x1;
}
#endif

181
drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ctxsw_prog_gp10b_h_
#define _hw_ctxsw_prog_gp10b_h_
static inline u32 ctxsw_prog_fecs_header_v(void)
{
return 0x00000100;
}
static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
{
return 0x00000008;
}
static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010;
}
static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
{
return 0x00000014;
}
static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
{
return 0x00000018;
}
static inline u32 ctxsw_prog_main_image_zcull_o(void)
{
return 0x0000001c;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
{
return 0x00000001;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
{
return 0x00000002;
}
static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
{
return 0x00000020;
}
static inline u32 ctxsw_prog_main_image_pm_o(void)
{
return 0x00000028;
}
static inline u32 ctxsw_prog_main_image_pm_mode_v(u32 r)
{
return (r >> 0) & 0x7;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_v(void)
{
return 0x00000000;
}
static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
{
return 0x0000002c;
}
static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
{
return 0x000000f4;
}
static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
{
return 0x000000f8;
}
static inline u32 ctxsw_prog_main_image_magic_value_o(void)
{
return 0x000000fc;
}
static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
{
return 0x600dc0de;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
{
return 0x0000000c;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
{
return 0x000000f4;
}
static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
{
return (r >> 16) & 0xffff;
}
static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
{
return 0x000000f8;
}
static inline u32 ctxsw_prog_local_magic_value_o(void)
{
return 0x000000fc;
}
static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
{
return 0xad0becab;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
{
return 0x000000ec;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
{
return (r >> 16) & 0xff;
}
static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
{
return 0x00000100;
}
static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
{
return 0x00000004;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
{
return 0x00000000;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
{
return 0x00000002;
}
#endif

221
drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_fb_gp10b_h_
#define _hw_fb_gp10b_h_
static inline u32 fb_fbhub_num_active_ltcs_r(void)
{
return 0x00100800;
}
static inline u32 fb_mmu_ctrl_r(void)
{
return 0x00100c80;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
{
return (v & 0x1) << 0;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
{
return 0x0;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
{
return (r >> 15) & 0x1;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
{
return 0x0;
}
static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16) & 0xff;
}
static inline u32 fb_mmu_invalidate_pdb_r(void)
{
return 0x00100cb8;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
{
return 0x0;
}
static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
{
return (v & 0xfffffff) << 4;
}
static inline u32 fb_mmu_invalidate_r(void)
{
return 0x00100cbc;
}
static inline u32 fb_mmu_invalidate_all_va_true_f(void)
{
return 0x1;
}
static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
{
return 0x2;
}
static inline u32 fb_mmu_invalidate_trigger_s(void)
{
return 1;
}
static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
{
return (v & 0x1) << 31;
}
static inline u32 fb_mmu_invalidate_trigger_m(void)
{
return 0x1 << 31;
}
static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
{
return (r >> 31) & 0x1;
}
static inline u32 fb_mmu_invalidate_trigger_true_f(void)
{
return 0x80000000;
}
static inline u32 fb_mmu_debug_wr_r(void)
{
return 0x00100cc8;
}
static inline u32 fb_mmu_debug_wr_aperture_s(void)
{
return 2;
}
static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
{
return (v & 0x3) << 0;
}
static inline u32 fb_mmu_debug_wr_aperture_m(void)
{
return 0x3 << 0;
}
static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
{
return (r >> 0) & 0x3;
}
static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
{
return 0x0;
}
static inline u32 fb_mmu_debug_wr_vol_false_f(void)
{
return 0x0;
}
static inline u32 fb_mmu_debug_wr_vol_true_v(void)
{
return 0x00000001;
}
static inline u32 fb_mmu_debug_wr_vol_true_f(void)
{
return 0x4;
}
static inline u32 fb_mmu_debug_wr_addr_v(u32 r)
{
return (r >> 4) & 0xfffffff;
}
static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
{
return 0x0000000c;
}
static inline u32 fb_mmu_debug_rd_r(void)
{
return 0x00100ccc;
}
static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
{
return 0x0;
}
static inline u32 fb_mmu_debug_rd_vol_false_f(void)
{
return 0x0;
}
static inline u32 fb_mmu_debug_rd_addr_v(u32 r)
{
return (r >> 4) & 0xfffffff;
}
static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
{
return 0x0000000c;
}
static inline u32 fb_mmu_debug_ctrl_r(void)
{
return 0x00100cc4;
}
static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
{
return (r >> 16) & 0x1;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
{
return 0x00000001;
}
static inline u32 fb_mmu_vpr_info_r(void)
{
return 0x00100cd0;
}
static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
{
return (v & 0x1) << 2;
}
static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
{
return 0x00000000;
}
static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
{
return 0x00000001;
}
#endif

509
drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h Normal file
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@@ -0,0 +1,509 @@
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_fifo_gp10b_h_
#define _hw_fifo_gp10b_h_
static inline u32 fifo_bar1_base_r(void)
{
return 0x00002254;
}
static inline u32 fifo_bar1_base_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
}
static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
{
return 0x0000000c;
}
static inline u32 fifo_bar1_base_valid_false_f(void)
{
return 0x0;
}
static inline u32 fifo_bar1_base_valid_true_f(void)
{
return 0x10000000;
}
static inline u32 fifo_runlist_base_r(void)
{
return 0x00002270;
}
static inline u32 fifo_runlist_base_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
}
static inline u32 fifo_runlist_base_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 fifo_runlist_r(void)
{
return 0x00002274;
}
static inline u32 fifo_runlist_engine_f(u32 v)
{
return (v & 0xf) << 20;
}
static inline u32 fifo_eng_runlist_base_r(u32 i)
{
return 0x00002280 + i*8;
}
static inline u32 fifo_eng_runlist_base__size_1_v(void)
{
return 0x00000001;
}
static inline u32 fifo_eng_runlist_r(u32 i)
{
return 0x00002284 + i*8;
}
static inline u32 fifo_eng_runlist__size_1_v(void)
{
return 0x00000001;
}
static inline u32 fifo_eng_runlist_length_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 fifo_eng_runlist_pending_true_f(void)
{
return 0x100000;
}
static inline u32 fifo_pb_timeslice_r(u32 i)
{
return 0x00002350 + i*4;
}
static inline u32 fifo_pb_timeslice_timeout_16_f(void)
{
return 0x10;
}
static inline u32 fifo_pb_timeslice_timescale_0_f(void)
{
return 0x0;
}
static inline u32 fifo_pb_timeslice_enable_true_f(void)
{
return 0x10000000;
}
static inline u32 fifo_pbdma_map_r(u32 i)
{
return 0x00002390 + i*4;
}
static inline u32 fifo_intr_0_r(void)
{
return 0x00002100;
}
static inline u32 fifo_intr_0_bind_error_pending_f(void)
{
return 0x1;
}
static inline u32 fifo_intr_0_bind_error_reset_f(void)
{
return 0x1;
}
static inline u32 fifo_intr_0_sched_error_pending_f(void)
{
return 0x100;
}
static inline u32 fifo_intr_0_sched_error_reset_f(void)
{
return 0x100;
}
static inline u32 fifo_intr_0_chsw_error_pending_f(void)
{
return 0x10000;
}
static inline u32 fifo_intr_0_chsw_error_reset_f(void)
{
return 0x10000;
}
static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
{
return 0x800000;
}
static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
{
return 0x800000;
}
static inline u32 fifo_intr_0_lb_error_pending_f(void)
{
return 0x1000000;
}
static inline u32 fifo_intr_0_lb_error_reset_f(void)
{
return 0x1000000;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
{
return 0x8000000;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
{
return 0x8000000;
}
static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
{
return 0x10000000;
}
static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
{
return 0x20000000;
}
static inline u32 fifo_intr_0_runlist_event_pending_f(void)
{
return 0x40000000;
}
static inline u32 fifo_intr_0_channel_intr_pending_f(void)
{
return 0x80000000;
}
static inline u32 fifo_intr_en_0_r(void)
{
return 0x00002140;
}
static inline u32 fifo_intr_en_1_r(void)
{
return 0x00002528;
}
static inline u32 fifo_intr_bind_error_r(void)
{
return 0x0000252c;
}
static inline u32 fifo_intr_sched_error_r(void)
{
return 0x0000254c;
}
static inline u32 fifo_intr_sched_error_code_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
{
return 0x0000000a;
}
static inline u32 fifo_intr_chsw_error_r(void)
{
return 0x0000256c;
}
static inline u32 fifo_intr_mmu_fault_id_r(void)
{
return 0x0000259c;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
{
return 0x00000000;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
{
return 0x0;
}
static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
{
return 0x00002800 + i*16;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
{
return (r >> 0) & 0xfffffff;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
{
return 0x0000000c;
}
static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
{
return 0x00002804 + i*16;
}
static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
{
return 0x00002808 + i*16;
}
static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
{
return 0x0000280c + i*16;
}
static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
{
return (r >> 0) & 0xf;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
{
return (r >> 6) & 0x1;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
{
return 0x00000000;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
{
return 0x00000001;
}
static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
{
return (r >> 8) & 0x3f;
}
static inline u32 fifo_intr_pbdma_id_r(void)
{
return 0x000025a0;
}
static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
{
return (v & 0x1) << (0 + i*1);
}
static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
{
return 0x00000001;
}
static inline u32 fifo_intr_runlist_r(void)
{
return 0x00002a00;
}
static inline u32 fifo_fb_timeout_r(void)
{
return 0x00002a04;
}
static inline u32 fifo_fb_timeout_period_m(void)
{
return 0x3fffffff << 0;
}
static inline u32 fifo_fb_timeout_period_max_f(void)
{
return 0x3fffffff;
}
static inline u32 fifo_error_sched_disable_r(void)
{
return 0x0000262c;
}
static inline u32 fifo_sched_disable_r(void)
{
return 0x00002630;
}
static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
{
return (v & 0x1) << (0 + i*1);
}
static inline u32 fifo_sched_disable_runlist_m(u32 i)
{
return 0x1 << (0 + i*1);
}
static inline u32 fifo_sched_disable_true_v(void)
{
return 0x00000001;
}
static inline u32 fifo_preempt_r(void)
{
return 0x00002634;
}
static inline u32 fifo_preempt_pending_true_f(void)
{
return 0x100000;
}
static inline u32 fifo_preempt_type_channel_f(void)
{
return 0x0;
}
static inline u32 fifo_preempt_chid_f(u32 v)
{
return (v & 0xfff) << 0;
}
static inline u32 fifo_trigger_mmu_fault_r(u32 i)
{
return 0x00002a30 + i*4;
}
static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
{
return (v & 0x1f) << 0;
}
static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
{
return (v & 0x1) << 8;
}
static inline u32 fifo_engine_status_r(u32 i)
{
return 0x00002640 + i*8;
}
static inline u32 fifo_engine_status__size_1_v(void)
{
return 0x00000002;
}
static inline u32 fifo_engine_status_id_v(u32 r)
{
return (r >> 0) & 0xfff;
}
static inline u32 fifo_engine_status_id_type_v(u32 r)
{
return (r >> 12) & 0x1;
}
static inline u32 fifo_engine_status_id_type_chid_v(void)
{
return 0x00000000;
}
static inline u32 fifo_engine_status_ctx_status_v(u32 r)
{
return (r >> 13) & 0x7;
}
static inline u32 fifo_engine_status_ctx_status_valid_v(void)
{
return 0x00000001;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
{
return 0x00000005;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
{
return 0x00000006;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
{
return 0x00000007;
}
static inline u32 fifo_engine_status_next_id_v(u32 r)
{
return (r >> 16) & 0xfff;
}
static inline u32 fifo_engine_status_next_id_type_v(u32 r)
{
return (r >> 28) & 0x1;
}
static inline u32 fifo_engine_status_next_id_type_chid_v(void)
{
return 0x00000000;
}
static inline u32 fifo_engine_status_faulted_v(u32 r)
{
return (r >> 30) & 0x1;
}
static inline u32 fifo_engine_status_faulted_true_v(void)
{
return 0x00000001;
}
static inline u32 fifo_engine_status_engine_v(u32 r)
{
return (r >> 31) & 0x1;
}
static inline u32 fifo_engine_status_engine_idle_v(void)
{
return 0x00000000;
}
static inline u32 fifo_engine_status_engine_busy_v(void)
{
return 0x00000001;
}
static inline u32 fifo_engine_status_ctxsw_v(u32 r)
{
return (r >> 15) & 0x1;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
{
return 0x00000001;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
{
return 0x8000;
}
static inline u32 fifo_pbdma_status_r(u32 i)
{
return 0x00003080 + i*4;
}
static inline u32 fifo_pbdma_status__size_1_v(void)
{
return 0x00000001;
}
static inline u32 fifo_pbdma_status_id_v(u32 r)
{
return (r >> 0) & 0xfff;
}
static inline u32 fifo_pbdma_status_id_type_v(u32 r)
{
return (r >> 12) & 0x1;
}
static inline u32 fifo_pbdma_status_id_type_chid_v(void)
{
return 0x00000000;
}
static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
{
return (r >> 13) & 0x7;
}
static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
{
return 0x00000001;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
{
return 0x00000005;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
{
return 0x00000006;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
{
return 0x00000007;
}
static inline u32 fifo_pbdma_status_next_id_v(u32 r)
{
return (r >> 16) & 0xfff;
}
static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
{
return (r >> 28) & 0x1;
}
static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
{
return 0x00000000;
}
static inline u32 fifo_pbdma_status_chsw_v(u32 r)
{
return (r >> 15) & 0x1;
}
static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
{
return 0x00000001;
}
#endif

141
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_flush_gp10b_h_
#define _hw_flush_gp10b_h_
static inline u32 flush_l2_system_invalidate_r(void)
{
return 0x00070004;
}
static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
{
return 0x00000001;
}
static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
{
return 0x1;
}
static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
{
return (r >> 1) & 0x1;
}
static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
{
return 0x00000001;
}
static inline u32 flush_l2_flush_dirty_r(void)
{
return 0x00070010;
}
static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
{
return 0x00000000;
}
static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
{
return 0x0;
}
static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
{
return 0x00000001;
}
static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
{
return 0x1;
}
static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
{
return (r >> 1) & 0x1;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
{
return 0x00000000;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
{
return 0x0;
}
static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
{
return 0x00000001;
}
static inline u32 flush_fb_flush_r(void)
{
return 0x00070000;
}
static inline u32 flush_fb_flush_pending_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 flush_fb_flush_pending_busy_v(void)
{
return 0x00000001;
}
static inline u32 flush_fb_flush_pending_busy_f(void)
{
return 0x1;
}
static inline u32 flush_fb_flush_outstanding_v(u32 r)
{
return (r >> 1) & 0x1;
}
static inline u32 flush_fb_flush_outstanding_true_v(void)
{
return 0x00000001;
}
#endif

57
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_fuse_gp10b_h_
#define _hw_fuse_gp10b_h_
static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
{
return 0x00021c38 + i*4;
}
#endif

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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ltc_gp10b_h_
#define _hw_ltc_gp10b_h_
static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
{
return 0x0014046c;
}
static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
{
return 0x00140518;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
{
return 0x0017e318;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
{
return 0x1 << 15;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
{
return 0x00140494;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
{
return (r >> 16) & 0x3;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
{
return 0x00000000;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
{
return 0x00000001;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
{
return 0x00000002;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
{
return 0x0017e26c;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
{
return 0x1;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
{
return 0x2;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
{
return 0x00000001;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
{
return 0x4;
}
static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
{
return 0x0017e26c;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
{
return 0x0017e270;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
{
return (v & 0x1ffff) << 0;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
{
return 0x0017e274;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
{
return (v & 0x1ffff) << 0;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
{
return 0x0001ffff;
}
static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
{
return 0x0017e278;
}
static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
{
return 0x0000000b;
}
static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
{
return (r >> 0) & 0x3ffffff;
}
static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
{
return 0x0017e27c;
}
static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
{
return 0x0017e000;
}
static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
{
return 0x0017e280;
}
static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
{
return (r >> 24) & 0xf;
}
static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
{
return (r >> 28) & 0xf;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
{
return 0x0017e2ac;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
{
return (v & 0x1f) << 16;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
{
return 0x0017e338;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
{
return (v & 0xf) << 0;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
{
return 0x0017e33c + i*4;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
{
return 0x00000004;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
{
return 0x0017e34c;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
{
return 32;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
{
return 0xffffffff << 0;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
{
return 0x0017e2b0;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
{
return 0x10000000;
}
static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
{
return 0x0017e214;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
{
return 0x1;
}
static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
{
return 0x00140214;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
{
return 0x1;
}
static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
{
return 0x00142214;
}
static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001;
}
static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
{
return 0x1;
}
static inline u32 ltc_ltc0_ltss_intr_r(void)
{
return 0x0014020c;
}
#endif

217
drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h Normal file
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@@ -0,0 +1,217 @@
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_mc_gp10b_h_
#define _hw_mc_gp10b_h_
static inline u32 mc_intr_0_r(void)
{
return 0x00000100;
}
static inline u32 mc_intr_0_pfifo_pending_f(void)
{
return 0x100;
}
static inline u32 mc_intr_0_pgraph_pending_f(void)
{
return 0x1000;
}
static inline u32 mc_intr_0_pmu_pending_f(void)
{
return 0x1000000;
}
static inline u32 mc_intr_0_ltc_pending_f(void)
{
return 0x2000000;
}
static inline u32 mc_intr_0_priv_ring_pending_f(void)
{
return 0x40000000;
}
static inline u32 mc_intr_0_pbus_pending_f(void)
{
return 0x10000000;
}
static inline u32 mc_intr_mask_0_r(void)
{
return 0x00000640;
}
static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
{
return 0x1000000;
}
static inline u32 mc_intr_en_0_r(void)
{
return 0x00000140;
}
static inline u32 mc_intr_en_0_inta_disabled_f(void)
{
return 0x0;
}
static inline u32 mc_intr_en_0_inta_hardware_f(void)
{
return 0x1;
}
static inline u32 mc_intr_en_1_r(void)
{
return 0x00000144;
}
static inline u32 mc_intr_en_1_inta_disabled_f(void)
{
return 0x0;
}
static inline u32 mc_enable_r(void)
{
return 0x00000200;
}
static inline u32 mc_enable_xbar_enabled_f(void)
{
return 0x4;
}
static inline u32 mc_enable_l2_enabled_f(void)
{
return 0x8;
}
static inline u32 mc_enable_pmedia_s(void)
{
return 1;
}
static inline u32 mc_enable_pmedia_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 mc_enable_pmedia_m(void)
{
return 0x1 << 4;
}
static inline u32 mc_enable_pmedia_v(u32 r)
{
return (r >> 4) & 0x1;
}
static inline u32 mc_enable_priv_ring_enabled_f(void)
{
return 0x20;
}
static inline u32 mc_enable_ce0_m(void)
{
return 0x1 << 6;
}
static inline u32 mc_enable_pfifo_enabled_f(void)
{
return 0x100;
}
static inline u32 mc_enable_pgraph_enabled_f(void)
{
return 0x1000;
}
static inline u32 mc_enable_pwr_v(u32 r)
{
return (r >> 13) & 0x1;
}
static inline u32 mc_enable_pwr_disabled_v(void)
{
return 0x00000000;
}
static inline u32 mc_enable_pwr_enabled_f(void)
{
return 0x2000;
}
static inline u32 mc_enable_pfb_enabled_f(void)
{
return 0x100000;
}
static inline u32 mc_enable_ce2_m(void)
{
return 0x1 << 21;
}
static inline u32 mc_enable_ce2_enabled_f(void)
{
return 0x200000;
}
static inline u32 mc_enable_blg_enabled_f(void)
{
return 0x8000000;
}
static inline u32 mc_enable_perfmon_enabled_f(void)
{
return 0x10000000;
}
static inline u32 mc_enable_hub_enabled_f(void)
{
return 0x20000000;
}
static inline u32 mc_enable_pb_r(void)
{
return 0x00000204;
}
static inline u32 mc_enable_pb_0_s(void)
{
return 1;
}
static inline u32 mc_enable_pb_0_f(u32 v)
{
return (v & 0x1) << 0;
}
static inline u32 mc_enable_pb_0_m(void)
{
return 0x1 << 0;
}
static inline u32 mc_enable_pb_0_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 mc_enable_pb_0_enabled_v(void)
{
return 0x00000001;
}
static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
{
return (v & 0x1) << (0 + i*1);
}
#endif

469
drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pbdma_gp10b_h_
#define _hw_pbdma_gp10b_h_
static inline u32 pbdma_gp_entry1_r(void)
{
return 0x10000004;
}
static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
{
return (r >> 0) & 0xff;
}
static inline u32 pbdma_gp_entry1_length_f(u32 v)
{
return (v & 0x1fffff) << 10;
}
static inline u32 pbdma_gp_entry1_length_v(u32 r)
{
return (r >> 10) & 0x1fffff;
}
static inline u32 pbdma_gp_base_r(u32 i)
{
return 0x00040048 + i*8192;
}
static inline u32 pbdma_gp_base__size_1_v(void)
{
return 0x00000001;
}
static inline u32 pbdma_gp_base_offset_f(u32 v)
{
return (v & 0x1fffffff) << 3;
}
static inline u32 pbdma_gp_base_rsvd_s(void)
{
return 3;
}
static inline u32 pbdma_gp_base_hi_r(u32 i)
{
return 0x0004004c + i*8192;
}
static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
{
return (v & 0x1f) << 16;
}
static inline u32 pbdma_gp_fetch_r(u32 i)
{
return 0x00040050 + i*8192;
}
static inline u32 pbdma_gp_get_r(u32 i)
{
return 0x00040014 + i*8192;
}
static inline u32 pbdma_gp_put_r(u32 i)
{
return 0x00040000 + i*8192;
}
static inline u32 pbdma_pb_fetch_r(u32 i)
{
return 0x00040054 + i*8192;
}
static inline u32 pbdma_pb_fetch_hi_r(u32 i)
{
return 0x00040058 + i*8192;
}
static inline u32 pbdma_get_r(u32 i)
{
return 0x00040018 + i*8192;
}
static inline u32 pbdma_get_hi_r(u32 i)
{
return 0x0004001c + i*8192;
}
static inline u32 pbdma_put_r(u32 i)
{
return 0x0004005c + i*8192;
}
static inline u32 pbdma_put_hi_r(u32 i)
{
return 0x00040060 + i*8192;
}
static inline u32 pbdma_formats_r(u32 i)
{
return 0x0004009c + i*8192;
}
static inline u32 pbdma_formats_gp_fermi0_f(void)
{
return 0x0;
}
static inline u32 pbdma_formats_pb_fermi1_f(void)
{
return 0x100;
}
static inline u32 pbdma_formats_mp_fermi0_f(void)
{
return 0x0;
}
static inline u32 pbdma_pb_header_r(u32 i)
{
return 0x00040084 + i*8192;
}
static inline u32 pbdma_pb_header_priv_user_f(void)
{
return 0x0;
}
static inline u32 pbdma_pb_header_method_zero_f(void)
{
return 0x0;
}
static inline u32 pbdma_pb_header_subchannel_zero_f(void)
{
return 0x0;
}
static inline u32 pbdma_pb_header_level_main_f(void)
{
return 0x0;
}
static inline u32 pbdma_pb_header_first_true_f(void)
{
return 0x400000;
}
static inline u32 pbdma_pb_header_type_inc_f(void)
{
return 0x20000000;
}
static inline u32 pbdma_subdevice_r(u32 i)
{
return 0x00040094 + i*8192;
}
static inline u32 pbdma_subdevice_id_f(u32 v)
{
return (v & 0xfff) << 0;
}
static inline u32 pbdma_subdevice_status_active_f(void)
{
return 0x10000000;
}
static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
{
return 0x20000000;
}
static inline u32 pbdma_method0_r(u32 i)
{
return 0x000400c0 + i*8192;
}
static inline u32 pbdma_data0_r(u32 i)
{
return 0x000400c4 + i*8192;
}
static inline u32 pbdma_target_r(u32 i)
{
return 0x000400ac + i*8192;
}
static inline u32 pbdma_target_engine_sw_f(void)
{
return 0x1f;
}
static inline u32 pbdma_acquire_r(u32 i)
{
return 0x00040030 + i*8192;
}
static inline u32 pbdma_acquire_retry_man_2_f(void)
{
return 0x2;
}
static inline u32 pbdma_acquire_retry_exp_2_f(void)
{
return 0x100;
}
static inline u32 pbdma_acquire_timeout_exp_max_f(void)
{
return 0x7800;
}
static inline u32 pbdma_acquire_timeout_man_max_f(void)
{
return 0x7fff8000;
}
static inline u32 pbdma_acquire_timeout_en_disable_f(void)
{
return 0x0;
}
static inline u32 pbdma_status_r(u32 i)
{
return 0x00040100 + i*8192;
}
static inline u32 pbdma_channel_r(u32 i)
{
return 0x00040120 + i*8192;
}
static inline u32 pbdma_signature_r(u32 i)
{
return 0x00040010 + i*8192;
}
static inline u32 pbdma_signature_hw_valid_f(void)
{
return 0xface;
}
static inline u32 pbdma_signature_sw_zero_f(void)
{
return 0x0;
}
static inline u32 pbdma_userd_r(u32 i)
{
return 0x00040008 + i*8192;
}
static inline u32 pbdma_userd_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 pbdma_userd_addr_f(u32 v)
{
return (v & 0x7fffff) << 9;
}
static inline u32 pbdma_userd_hi_r(u32 i)
{
return 0x0004000c + i*8192;
}
static inline u32 pbdma_userd_hi_addr_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 pbdma_hce_ctrl_r(u32 i)
{
return 0x000400e4 + i*8192;
}
static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
{
return 0x20;
}
static inline u32 pbdma_intr_0_r(u32 i)
{
return 0x00040108 + i*8192;
}
static inline u32 pbdma_intr_0_memreq_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 pbdma_intr_0_memreq_pending_f(void)
{
return 0x1;
}
static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
{
return 0x2;
}
static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
{
return 0x4;
}
static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
{
return 0x8;
}
static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
{
return 0x10;
}
static inline u32 pbdma_intr_0_memflush_pending_f(void)
{
return 0x20;
}
static inline u32 pbdma_intr_0_memop_pending_f(void)
{
return 0x40;
}
static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
{
return 0x80;
}
static inline u32 pbdma_intr_0_lbreq_pending_f(void)
{
return 0x100;
}
static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
{
return 0x200;
}
static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
{
return 0x400;
}
static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
{
return 0x800;
}
static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
{
return 0x1000;
}
static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
{
return 0x2000;
}
static inline u32 pbdma_intr_0_gpptr_pending_f(void)
{
return 0x4000;
}
static inline u32 pbdma_intr_0_gpentry_pending_f(void)
{
return 0x8000;
}
static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
{
return 0x10000;
}
static inline u32 pbdma_intr_0_pbptr_pending_f(void)
{
return 0x20000;
}
static inline u32 pbdma_intr_0_pbentry_pending_f(void)
{
return 0x40000;
}
static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
{
return 0x80000;
}
static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
{
return 0x100000;
}
static inline u32 pbdma_intr_0_method_pending_f(void)
{
return 0x200000;
}
static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
{
return 0x400000;
}
static inline u32 pbdma_intr_0_device_pending_f(void)
{
return 0x800000;
}
static inline u32 pbdma_intr_0_semaphore_pending_f(void)
{
return 0x2000000;
}
static inline u32 pbdma_intr_0_acquire_pending_f(void)
{
return 0x4000000;
}
static inline u32 pbdma_intr_0_pri_pending_f(void)
{
return 0x8000000;
}
static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
{
return 0x20000000;
}
static inline u32 pbdma_intr_0_pbseg_pending_f(void)
{
return 0x40000000;
}
static inline u32 pbdma_intr_0_signature_pending_f(void)
{
return 0x80000000;
}
static inline u32 pbdma_intr_1_r(u32 i)
{
return 0x00040148 + i*8192;
}
static inline u32 pbdma_intr_en_0_r(u32 i)
{
return 0x0004010c + i*8192;
}
static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
{
return 0x100;
}
static inline u32 pbdma_intr_en_1_r(u32 i)
{
return 0x0004014c + i*8192;
}
static inline u32 pbdma_intr_stall_r(u32 i)
{
return 0x0004013c + i*8192;
}
static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
{
return 0x100;
}
static inline u32 pbdma_udma_nop_r(void)
{
return 0x00000008;
}
static inline u32 pbdma_syncpointa_r(u32 i)
{
return 0x000400a4 + i*8192;
}
static inline u32 pbdma_syncpointa_payload_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 pbdma_syncpointb_r(u32 i)
{
return 0x000400a8 + i*8192;
}
static inline u32 pbdma_syncpointb_op_v(u32 r)
{
return (r >> 0) & 0x3;
}
static inline u32 pbdma_syncpointb_op_wait_v(void)
{
return 0x00000000;
}
static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
{
return (r >> 4) & 0x1;
}
static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
{
return 0x00000001;
}
static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
{
return (r >> 8) & 0xff;
}
#endif

145
drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pri_ringmaster_gp10b_h_
#define _hw_pri_ringmaster_gp10b_h_
static inline u32 pri_ringmaster_command_r(void)
{
return 0x0012004c;
}
static inline u32 pri_ringmaster_command_cmd_m(void)
{
return 0x3f << 0;
}
static inline u32 pri_ringmaster_command_cmd_v(u32 r)
{
return (r >> 0) & 0x3f;
}
static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
{
return 0x00000000;
}
static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
{
return 0x1;
}
static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
{
return 0x2;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
{
return 0x3;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
{
return 0x0;
}
static inline u32 pri_ringmaster_command_data_r(void)
{
return 0x00120048;
}
static inline u32 pri_ringmaster_start_results_r(void)
{
return 0x00120050;
}
static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
{
return 0x00000001;
}
static inline u32 pri_ringmaster_intr_status0_r(void)
{
return 0x00120058;
}
static inline u32 pri_ringmaster_intr_status1_r(void)
{
return 0x0012005c;
}
static inline u32 pri_ringmaster_global_ctl_r(void)
{
return 0x00120060;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
{
return 0x1;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
{
return 0x0;
}
static inline u32 pri_ringmaster_enum_fbp_r(void)
{
return 0x00120074;
}
static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
{
return (r >> 0) & 0x1f;
}
static inline u32 pri_ringmaster_enum_gpc_r(void)
{
return 0x00120078;
}
static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
{
return (r >> 0) & 0x1f;
}
static inline u32 pri_ringmaster_enum_ltc_r(void)
{
return 0x0012006c;
}
static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
{
return (r >> 0) & 0x1f;
}
#endif

69
drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pri_ringstation_sys_gp10b_h_
#define _hw_pri_ringstation_sys_gp10b_h_
static inline u32 pri_ringstation_sys_master_config_r(u32 i)
{
return 0x00122300 + i*4;
}
static inline u32 pri_ringstation_sys_decode_config_r(void)
{
return 0x00122204;
}
static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
{
return 0x7 << 0;
}
static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
{
return 0x1;
}
#endif

141
drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_proj_gp10b_h_
#define _hw_proj_gp10b_h_
static inline u32 proj_gpc_base_v(void)
{
return 0x00500000;
}
static inline u32 proj_gpc_shared_base_v(void)
{
return 0x00418000;
}
static inline u32 proj_gpc_stride_v(void)
{
return 0x00008000;
}
static inline u32 proj_ltc_stride_v(void)
{
return 0x00002000;
}
static inline u32 proj_lts_stride_v(void)
{
return 0x00000200;
}
static inline u32 proj_ppc_in_gpc_base_v(void)
{
return 0x00003000;
}
static inline u32 proj_ppc_in_gpc_stride_v(void)
{
return 0x00000200;
}
static inline u32 proj_rop_base_v(void)
{
return 0x00410000;
}
static inline u32 proj_rop_shared_base_v(void)
{
return 0x00408800;
}
static inline u32 proj_rop_stride_v(void)
{
return 0x00000400;
}
static inline u32 proj_tpc_in_gpc_base_v(void)
{
return 0x00004000;
}
static inline u32 proj_tpc_in_gpc_stride_v(void)
{
return 0x00000800;
}
static inline u32 proj_tpc_in_gpc_shared_base_v(void)
{
return 0x00001800;
}
static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000001;
}
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
{
return 0x00000002;
}
static inline u32 proj_scal_litter_num_fbps_v(void)
{
return 0x00000001;
}
static inline u32 proj_scal_litter_num_gpcs_v(void)
{
return 0x00000001;
}
static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
{
return 0x00000001;
}
static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
{
return 0x00000002;
}
static inline u32 proj_scal_litter_num_zcull_banks_v(void)
{
return 0x00000004;
}
static inline u32 proj_scal_max_gpcs_v(void)
{
return 0x00000020;
}
static inline u32 proj_scal_max_tpc_per_gpc_v(void)
{
return 0x00000008;
}
#endif

805
drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pwr_gp10b_h_
#define _hw_pwr_gp10b_h_
static inline u32 pwr_falcon_irqsset_r(void)
{
return 0x0010a000;
}
static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
{
return 0x40;
}
static inline u32 pwr_falcon_irqsclr_r(void)
{
return 0x0010a004;
}
static inline u32 pwr_falcon_irqstat_r(void)
{
return 0x0010a008;
}
static inline u32 pwr_falcon_irqstat_halt_true_f(void)
{
return 0x10;
}
static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
{
return 0x20;
}
static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
{
return 0x40;
}
static inline u32 pwr_falcon_irqmode_r(void)
{
return 0x0010a00c;
}
static inline u32 pwr_falcon_irqmset_r(void)
{
return 0x0010a010;
}
static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
{
return (v & 0x1) << 0;
}
static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
{
return (v & 0x1) << 1;
}
static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
{
return (v & 0x1) << 2;
}
static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
{
return (v & 0x1) << 3;
}
static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
{
return (v & 0x1) << 5;
}
static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
{
return (v & 0x1) << 6;
}
static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
{
return (v & 0x1) << 7;
}
static inline u32 pwr_falcon_irqmclr_r(void)
{
return 0x0010a014;
}
static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
{
return (v & 0x1) << 0;
}
static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
{
return (v & 0x1) << 1;
}
static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
{
return (v & 0x1) << 2;
}
static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
{
return (v & 0x1) << 3;
}
static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
{
return (v & 0x1) << 5;
}
static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
{
return (v & 0x1) << 6;
}
static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
{
return (v & 0x1) << 7;
}
static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
{
return (v & 0xff) << 8;
}
static inline u32 pwr_falcon_irqmask_r(void)
{
return 0x0010a018;
}
static inline u32 pwr_falcon_irqdest_r(void)
{
return 0x0010a01c;
}
static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
{
return (v & 0x1) << 0;
}
static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
{
return (v & 0x1) << 1;
}
static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
{
return (v & 0x1) << 2;
}
static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
{
return (v & 0x1) << 3;
}
static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
{
return (v & 0x1) << 5;
}
static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
{
return (v & 0x1) << 6;
}
static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
{
return (v & 0x1) << 7;
}
static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
{
return (v & 0xff) << 8;
}
static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
{
return (v & 0x1) << 16;
}
static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
{
return (v & 0x1) << 17;
}
static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
{
return (v & 0x1) << 18;
}
static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
{
return (v & 0x1) << 19;
}
static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
{
return (v & 0x1) << 20;
}
static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
{
return (v & 0x1) << 21;
}
static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
{
return (v & 0x1) << 22;
}
static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
{
return (v & 0x1) << 23;
}
static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
{
return (v & 0xff) << 24;
}
static inline u32 pwr_falcon_curctx_r(void)
{
return 0x0010a050;
}
static inline u32 pwr_falcon_nxtctx_r(void)
{
return 0x0010a054;
}
static inline u32 pwr_falcon_mailbox0_r(void)
{
return 0x0010a040;
}
static inline u32 pwr_falcon_mailbox1_r(void)
{
return 0x0010a044;
}
static inline u32 pwr_falcon_itfen_r(void)
{
return 0x0010a048;
}
static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
{
return 0x1;
}
static inline u32 pwr_falcon_idlestate_r(void)
{
return 0x0010a04c;
}
static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
{
return (r >> 1) & 0x7fff;
}
static inline u32 pwr_falcon_os_r(void)
{
return 0x0010a080;
}
static inline u32 pwr_falcon_engctl_r(void)
{
return 0x0010a0a4;
}
static inline u32 pwr_falcon_cpuctl_r(void)
{
return 0x0010a100;
}
static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
{
return (v & 0x1) << 1;
}
static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
{
return 0x1 << 4;
}
static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
{
return (r >> 4) & 0x1;
}
static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
{
return (v & 0x1) << 6;
}
static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
{
return 0x1 << 6;
}
static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
{
return (r >> 6) & 0x1;
}
static inline u32 pwr_falcon_cpuctl_alias_r(void)
{
return 0x0010a130;
}
static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
{
return (v & 0x1) << 1;
}
static inline u32 pwr_pmu_scpctl_stat_r(void)
{
return 0x0010ac08;
}
static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
{
return (v & 0x1) << 20;
}
static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
{
return 0x1 << 20;
}
static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
{
return (r >> 20) & 0x1;
}
static inline u32 pwr_falcon_imemc_r(u32 i)
{
return 0x0010a180 + i*16;
}
static inline u32 pwr_falcon_imemc_offs_f(u32 v)
{
return (v & 0x3f) << 2;
}
static inline u32 pwr_falcon_imemc_blk_f(u32 v)
{
return (v & 0xff) << 8;
}
static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
{
return (v & 0x1) << 24;
}
static inline u32 pwr_falcon_imemd_r(u32 i)
{
return 0x0010a184 + i*16;
}
static inline u32 pwr_falcon_imemt_r(u32 i)
{
return 0x0010a188 + i*16;
}
static inline u32 pwr_falcon_sctl_r(void)
{
return 0x0010a240;
}
static inline u32 pwr_falcon_mmu_phys_sec_r(void)
{
return 0x00100ce4;
}
static inline u32 pwr_falcon_bootvec_r(void)
{
return 0x0010a104;
}
static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 pwr_falcon_hwcfg_r(void)
{
return 0x0010a108;
}
static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
{
return (r >> 0) & 0x1ff;
}
static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
{
return (r >> 9) & 0x1ff;
}
static inline u32 pwr_falcon_dmatrfbase_r(void)
{
return 0x0010a110;
}
static inline u32 pwr_falcon_dmatrfmoffs_r(void)
{
return 0x0010a114;
}
static inline u32 pwr_falcon_dmatrfcmd_r(void)
{
return 0x0010a118;
}
static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
{
return (v & 0x1) << 5;
}
static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
{
return (v & 0x7) << 8;
}
static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
{
return (v & 0x7) << 12;
}
static inline u32 pwr_falcon_dmatrffboffs_r(void)
{
return 0x0010a11c;
}
static inline u32 pwr_falcon_exterraddr_r(void)
{
return 0x0010a168;
}
static inline u32 pwr_falcon_exterrstat_r(void)
{
return 0x0010a16c;
}
static inline u32 pwr_falcon_exterrstat_valid_m(void)
{
return 0x1 << 31;
}
static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
{
return (r >> 31) & 0x1;
}
static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
{
return 0x00000001;
}
static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
{
return 0x0010a200;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
{
return 4;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
{
return (v & 0xf) << 0;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
{
return 0xf << 0;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
{
return (r >> 0) & 0xf;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
{
return 0x8;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
{
return 0xe;
}
static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
{
return (v & 0x1f) << 8;
}
static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
{
return 0x0010a20c;
}
static inline u32 pwr_falcon_dmemc_r(u32 i)
{
return 0x0010a1c0 + i*8;
}
static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
{
return (v & 0x3f) << 2;
}
static inline u32 pwr_falcon_dmemc_offs_m(void)
{
return 0x3f << 2;
}
static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
{
return (v & 0xff) << 8;
}
static inline u32 pwr_falcon_dmemc_blk_m(void)
{
return 0xff << 8;
}
static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
{
return (v & 0x1) << 24;
}
static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
{
return (v & 0x1) << 25;
}
static inline u32 pwr_falcon_dmemd_r(u32 i)
{
return 0x0010a1c4 + i*8;
}
static inline u32 pwr_pmu_new_instblk_r(void)
{
return 0x0010a480;
}
static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
}
static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
{
return 0x0;
}
static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
{
return 0x20000000;
}
static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
{
return (v & 0x1) << 30;
}
static inline u32 pwr_pmu_mutex_id_r(void)
{
return 0x0010a488;
}
static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
{
return (r >> 0) & 0xff;
}
static inline u32 pwr_pmu_mutex_id_value_init_v(void)
{
return 0x00000000;
}
static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
{
return 0x000000ff;
}
static inline u32 pwr_pmu_mutex_id_release_r(void)
{
return 0x0010a48c;
}
static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 pwr_pmu_mutex_id_release_value_m(void)
{
return 0xff << 0;
}
static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
{
return 0x00000000;
}
static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
{
return 0x0;
}
static inline u32 pwr_pmu_mutex_r(u32 i)
{
return 0x0010a580 + i*4;
}
static inline u32 pwr_pmu_mutex__size_1_v(void)
{
return 0x00000010;
}
static inline u32 pwr_pmu_mutex_value_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 pwr_pmu_mutex_value_v(u32 r)
{
return (r >> 0) & 0xff;
}
static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
{
return 0x0;
}
static inline u32 pwr_pmu_queue_head_r(u32 i)
{
return 0x0010a4a0 + i*4;
}
static inline u32 pwr_pmu_queue_head__size_1_v(void)
{
return 0x00000004;
}
static inline u32 pwr_pmu_queue_head_address_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 pwr_pmu_queue_head_address_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 pwr_pmu_queue_tail_r(u32 i)
{
return 0x0010a4b0 + i*4;
}
static inline u32 pwr_pmu_queue_tail__size_1_v(void)
{
return 0x00000004;
}
static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 pwr_pmu_msgq_head_r(void)
{
return 0x0010a4c8;
}
static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 pwr_pmu_msgq_tail_r(void)
{
return 0x0010a4cc;
}
static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 pwr_pmu_idle_mask_r(u32 i)
{
return 0x0010a504 + i*16;
}
static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
{
return 0x1;
}
static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
{
return 0x200000;
}
static inline u32 pwr_pmu_idle_count_r(u32 i)
{
return 0x0010a508 + i*16;
}
static inline u32 pwr_pmu_idle_count_value_f(u32 v)
{
return (v & 0x7fffffff) << 0;
}
static inline u32 pwr_pmu_idle_count_value_v(u32 r)
{
return (r >> 0) & 0x7fffffff;
}
static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
{
return (v & 0x1) << 31;
}
static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
{
return 0x0010a50c + i*16;
}
static inline u32 pwr_pmu_idle_ctrl_value_m(void)
{
return 0x3 << 0;
}
static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
{
return 0x2;
}
static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
{
return 0x3;
}
static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
{
return 0x1 << 2;
}
static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
{
return 0x0;
}
static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
{
return 0x0010a9f0 + i*8;
}
static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
{
return 0x0010a9f4 + i*8;
}
static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
{
return 0x0010aa30 + i*8;
}
static inline u32 pwr_pmu_debug_r(u32 i)
{
return 0x0010a5c0 + i*4;
}
static inline u32 pwr_pmu_debug__size_1_v(void)
{
return 0x00000004;
}
static inline u32 pwr_pmu_mailbox_r(u32 i)
{
return 0x0010a450 + i*4;
}
static inline u32 pwr_pmu_mailbox__size_1_v(void)
{
return 0x0000000c;
}
static inline u32 pwr_pmu_bar0_addr_r(void)
{
return 0x0010a7a0;
}
static inline u32 pwr_pmu_bar0_data_r(void)
{
return 0x0010a7a4;
}
static inline u32 pwr_pmu_bar0_ctl_r(void)
{
return 0x0010a7ac;
}
static inline u32 pwr_pmu_bar0_timeout_r(void)
{
return 0x0010a7a8;
}
static inline u32 pwr_pmu_bar0_fecs_error_r(void)
{
return 0x0010a988;
}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0 + i*4;
}
static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
{
return 0x0010a6e8 + i*4;
}
static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
{
return 0x0010a710 + i*4;
}
static inline u32 pwr_pmu_pg_intren_r(u32 i)
{
return 0x0010a760 + i*4;
}
static inline u32 pwr_fbif_transcfg_r(u32 i)
{
return 0x0010ae00 + i*4;
}
static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
{
return 0x0;
}
static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
{
return 0x1;
}
static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
{
return 0x2;
}
static inline u32 pwr_fbif_transcfg_mem_type_s(void)
{
return 1;
}
static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
{
return (v & 0x1) << 2;
}
static inline u32 pwr_fbif_transcfg_mem_type_m(void)
{
return 0x1 << 2;
}
static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
{
return 0x0;
}
static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
{
return 0x4;
}
#endif

385
drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h Normal file
View File

@@ -0,0 +1,385 @@
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ram_gp10b_h_
#define _hw_ram_gp10b_h_
static inline u32 ram_in_ramfc_s(void)
{
return 4096;
}
static inline u32 ram_in_ramfc_w(void)
{
return 0;
}
static inline u32 ram_in_page_dir_base_target_f(u32 v)
{
return (v & 0x3) << 0;
}
static inline u32 ram_in_page_dir_base_target_w(void)
{
return 128;
}
static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 ram_in_page_dir_base_vol_w(void)
{
return 128;
}
static inline u32 ram_in_page_dir_base_vol_true_f(void)
{
return 0x4;
}
static inline u32 ram_in_page_dir_base_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
}
static inline u32 ram_in_page_dir_base_lo_w(void)
{
return 128;
}
static inline u32 ram_in_page_dir_base_hi_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 ram_in_page_dir_base_hi_w(void)
{
return 129;
}
static inline u32 ram_in_adr_limit_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
}
static inline u32 ram_in_adr_limit_lo_w(void)
{
return 130;
}
static inline u32 ram_in_adr_limit_hi_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 ram_in_adr_limit_hi_w(void)
{
return 131;
}
static inline u32 ram_in_engine_cs_w(void)
{
return 132;
}
static inline u32 ram_in_engine_cs_wfi_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_engine_cs_wfi_f(void)
{
return 0x0;
}
static inline u32 ram_in_engine_cs_fg_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_engine_cs_fg_f(void)
{
return 0x8;
}
static inline u32 ram_in_gr_cs_w(void)
{
return 132;
}
static inline u32 ram_in_gr_cs_wfi_f(void)
{
return 0x0;
}
static inline u32 ram_in_gr_wfi_target_w(void)
{
return 132;
}
static inline u32 ram_in_gr_wfi_mode_w(void)
{
return 132;
}
static inline u32 ram_in_gr_wfi_mode_physical_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_gr_wfi_mode_physical_f(void)
{
return 0x0;
}
static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
{
return 0x4;
}
static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
}
static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
{
return 132;
}
static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
{
return 133;
}
static inline u32 ram_in_base_shift_v(void)
{
return 0x0000000c;
}
static inline u32 ram_in_alloc_size_v(void)
{
return 0x00001000;
}
static inline u32 ram_fc_size_val_v(void)
{
return 0x00000200;
}
static inline u32 ram_fc_gp_put_w(void)
{
return 0;
}
static inline u32 ram_fc_userd_w(void)
{
return 2;
}
static inline u32 ram_fc_userd_hi_w(void)
{
return 3;
}
static inline u32 ram_fc_signature_w(void)
{
return 4;
}
static inline u32 ram_fc_gp_get_w(void)
{
return 5;
}
static inline u32 ram_fc_pb_get_w(void)
{
return 6;
}
static inline u32 ram_fc_pb_get_hi_w(void)
{
return 7;
}
static inline u32 ram_fc_pb_top_level_get_w(void)
{
return 8;
}
static inline u32 ram_fc_pb_top_level_get_hi_w(void)
{
return 9;
}
static inline u32 ram_fc_acquire_w(void)
{
return 12;
}
static inline u32 ram_fc_semaphorea_w(void)
{
return 14;
}
static inline u32 ram_fc_semaphoreb_w(void)
{
return 15;
}
static inline u32 ram_fc_semaphorec_w(void)
{
return 16;
}
static inline u32 ram_fc_semaphored_w(void)
{
return 17;
}
static inline u32 ram_fc_gp_base_w(void)
{
return 18;
}
static inline u32 ram_fc_gp_base_hi_w(void)
{
return 19;
}
static inline u32 ram_fc_gp_fetch_w(void)
{
return 20;
}
static inline u32 ram_fc_pb_fetch_w(void)
{
return 21;
}
static inline u32 ram_fc_pb_fetch_hi_w(void)
{
return 22;
}
static inline u32 ram_fc_pb_put_w(void)
{
return 23;
}
static inline u32 ram_fc_pb_put_hi_w(void)
{
return 24;
}
static inline u32 ram_fc_pb_header_w(void)
{
return 33;
}
static inline u32 ram_fc_pb_count_w(void)
{
return 34;
}
static inline u32 ram_fc_subdevice_w(void)
{
return 37;
}
static inline u32 ram_fc_formats_w(void)
{
return 39;
}
static inline u32 ram_fc_syncpointa_w(void)
{
return 41;
}
static inline u32 ram_fc_syncpointb_w(void)
{
return 42;
}
static inline u32 ram_fc_target_w(void)
{
return 43;
}
static inline u32 ram_fc_hce_ctrl_w(void)
{
return 57;
}
static inline u32 ram_fc_chid_w(void)
{
return 58;
}
static inline u32 ram_fc_chid_id_f(u32 v)
{
return (v & 0xfff) << 0;
}
static inline u32 ram_fc_chid_id_w(void)
{
return 0;
}
static inline u32 ram_fc_pb_timeslice_w(void)
{
return 62;
}
static inline u32 ram_userd_base_shift_v(void)
{
return 0x00000009;
}
static inline u32 ram_userd_chan_size_v(void)
{
return 0x00000200;
}
static inline u32 ram_userd_put_w(void)
{
return 16;
}
static inline u32 ram_userd_get_w(void)
{
return 17;
}
static inline u32 ram_userd_ref_w(void)
{
return 18;
}
static inline u32 ram_userd_put_hi_w(void)
{
return 19;
}
static inline u32 ram_userd_ref_threshold_w(void)
{
return 20;
}
static inline u32 ram_userd_top_level_get_w(void)
{
return 22;
}
static inline u32 ram_userd_top_level_get_hi_w(void)
{
return 23;
}
static inline u32 ram_userd_get_hi_w(void)
{
return 24;
}
static inline u32 ram_userd_gp_get_w(void)
{
return 34;
}
static inline u32 ram_userd_gp_put_w(void)
{
return 35;
}
static inline u32 ram_userd_gp_top_level_get_w(void)
{
return 22;
}
static inline u32 ram_userd_gp_top_level_get_hi_w(void)
{
return 23;
}
static inline u32 ram_rl_entry_size_v(void)
{
return 0x00000008;
}
#endif

217
drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_therm_gp10b_h_
#define _hw_therm_gp10b_h_
static inline u32 therm_use_a_r(void)
{
return 0x00020798;
}
static inline u32 therm_evt_ext_therm_0_r(void)
{
return 0x00020700;
}
static inline u32 therm_evt_ext_therm_1_r(void)
{
return 0x00020704;
}
static inline u32 therm_evt_ext_therm_2_r(void)
{
return 0x00020708;
}
static inline u32 therm_weight_1_r(void)
{
return 0x00020024;
}
static inline u32 therm_peakpower_config1_r(u32 i)
{
return 0x00020154 + i*4;
}
static inline u32 therm_peakpower_config1_window_period_2m_v(void)
{
return 0x00000015;
}
static inline u32 therm_peakpower_config1_window_period_2m_f(void)
{
return 0x15;
}
static inline u32 therm_peakpower_config1_window_en_enabled_f(void)
{
return 0x80000000;
}
static inline u32 therm_peakpower_config1_r(u32 i)
{
return 0x000202e8 + i*4;
}
static inline u32 therm_peakpower_config1_ba_sum_shift_s(void)
{
return 5;
}
static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v)
{
return (v & 0x1f) << 8;
}
static inline u32 therm_peakpower_config1_ba_sum_shift_m(void)
{
return 0x1f << 8;
}
static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r)
{
return (r >> 8) & 0x1f;
}
static inline u32 therm_peakpower_config2_r(u32 i)
{
return 0x00020170 + i*4;
}
static inline u32 therm_peakpower_config4_r(u32 i)
{
return 0x000201c0 + i*4;
}
static inline u32 therm_peakpower_config8_r(u32 i)
{
return 0x000202e8 + i*4;
}
static inline u32 therm_peakpower_config9_r(u32 i)
{
return 0x000202f4 + i*4;
}
static inline u32 therm_config1_r(void)
{
return 0x00020050;
}
static inline u32 therm_gate_ctrl_r(u32 i)
{
return 0x00020200 + i*4;
}
static inline u32 therm_gate_ctrl_eng_clk_m(void)
{
return 0x3 << 0;
}
static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
{
return 0x0;
}
static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
{
return 0x1;
}
static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
{
return 0x2;
}
static inline u32 therm_gate_ctrl_blk_clk_m(void)
{
return 0x3 << 2;
}
static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
{
return 0x0;
}
static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
{
return 0x4;
}
static inline u32 therm_gate_ctrl_eng_pwr_m(void)
{
return 0x3 << 4;
}
static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
{
return 0x10;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
{
return 0x00000002;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
{
return 0x20;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
{
return (v & 0x1f) << 8;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
{
return 0x1f << 8;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
{
return (v & 0x7) << 13;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
{
return 0x7 << 13;
}
static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
{
return (v & 0xf) << 20;
}
static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
{
return 0xf << 20;
}
static inline u32 therm_fecs_idle_filter_r(void)
{
return 0x00020288;
}
static inline u32 therm_fecs_idle_filter_value_m(void)
{
return 0xffffffff << 0;
}
static inline u32 therm_hubmmu_idle_filter_r(void)
{
return 0x0002028c;
}
static inline u32 therm_hubmmu_idle_filter_value_m(void)
{
return 0xffffffff << 0;
}
#endif

101
drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_timer_gp10b_h_
#define _hw_timer_gp10b_h_
static inline u32 timer_pri_timeout_r(void)
{
return 0x00009080;
}
static inline u32 timer_pri_timeout_period_f(u32 v)
{
return (v & 0xffffff) << 0;
}
static inline u32 timer_pri_timeout_period_m(void)
{
return 0xffffff << 0;
}
static inline u32 timer_pri_timeout_period_v(u32 r)
{
return (r >> 0) & 0xffffff;
}
static inline u32 timer_pri_timeout_en_f(u32 v)
{
return (v & 0x1) << 31;
}
static inline u32 timer_pri_timeout_en_m(void)
{
return 0x1 << 31;
}
static inline u32 timer_pri_timeout_en_v(u32 r)
{
return (r >> 31) & 0x1;
}
static inline u32 timer_pri_timeout_en_en_enabled_f(void)
{
return 0x80000000;
}
static inline u32 timer_pri_timeout_en_en_disabled_f(void)
{
return 0x0;
}
static inline u32 timer_pri_timeout_save_0_r(void)
{
return 0x00009084;
}
static inline u32 timer_pri_timeout_save_1_r(void)
{
return 0x00009088;
}
static inline u32 timer_pri_timeout_fecs_errcode_r(void)
{
return 0x0000908c;
}
#endif

137
drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_top_gp10b_h_
#define _hw_top_gp10b_h_
static inline u32 top_num_gpcs_r(void)
{
return 0x00022430;
}
static inline u32 top_num_gpcs_value_v(u32 r)
{
return (r >> 0) & 0x1f;
}
static inline u32 top_tpc_per_gpc_r(void)
{
return 0x00022434;
}
static inline u32 top_tpc_per_gpc_value_v(u32 r)
{
return (r >> 0) & 0x1f;
}
static inline u32 top_num_fbps_r(void)
{
return 0x00022438;
}
static inline u32 top_num_fbps_value_v(u32 r)
{
return (r >> 0) & 0x1f;
}
static inline u32 top_num_ltcs_r(void)
{
return 0x00022454;
}
static inline u32 top_device_info_r(u32 i)
{
return 0x00022700 + i*4;
}
static inline u32 top_device_info__size_1_v(void)
{
return 0x00000040;
}
static inline u32 top_device_info_chain_v(u32 r)
{
return (r >> 31) & 0x1;
}
static inline u32 top_device_info_chain_enable_v(void)
{
return 0x00000001;
}
static inline u32 top_device_info_engine_enum_v(u32 r)
{
return (r >> 26) & 0xf;
}
static inline u32 top_device_info_runlist_enum_v(u32 r)
{
return (r >> 21) & 0xf;
}
static inline u32 top_device_info_type_enum_v(u32 r)
{
return (r >> 2) & 0x1fffffff;
}
static inline u32 top_device_info_type_enum_graphics_v(void)
{
return 0x00000000;
}
static inline u32 top_device_info_type_enum_graphics_f(void)
{
return 0x0;
}
static inline u32 top_device_info_type_enum_copy0_v(void)
{
return 0x00000001;
}
static inline u32 top_device_info_type_enum_copy0_f(void)
{
return 0x4;
}
static inline u32 top_device_info_entry_v(u32 r)
{
return (r >> 0) & 0x3;
}
static inline u32 top_device_info_entry_not_valid_v(void)
{
return 0x00000000;
}
static inline u32 top_device_info_entry_enum_v(void)
{
return 0x00000002;
}
#endif

289
drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_trim_gp10b_h_
#define _hw_trim_gp10b_h_
static inline u32 trim_sys_gpcpll_cfg_r(void)
{
return 0x00137000;
}
static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
{
return 0x1 << 0;
}
static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
{
return 0x0;
}
static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
{
return 0x1;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
{
return 0x1 << 1;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
{
return (r >> 1) & 0x1;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
{
return 0x00000000;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
{
return 0x1 << 4;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
{
return 0x0;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
{
return 0x10;
}
static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
{
return (r >> 17) & 0x1;
}
static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
{
return 0x20000;
}
static inline u32 trim_sys_gpcpll_coeff_r(void)
{
return 0x00137004;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
{
return (r >> 0) & 0xff;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
{
return (v & 0xff) << 8;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
{
return 0xff << 8;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
{
return (r >> 8) & 0xff;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
{
return (v & 0x3f) << 16;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
{
return (r >> 16) & 0x3f;
}
static inline u32 trim_sys_sel_vco_r(void)
{
return 0x00137100;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
{
return 0x1 << 0;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
{
return 0x00000000;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
{
return 0x0;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
{
return 0x0;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
{
return 0x1;
}
static inline u32 trim_sys_gpc2clk_out_r(void)
{
return 0x00137250;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
{
return 6;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
{
return (v & 0x3f) << 0;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
{
return 0x3f << 0;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
{
return (r >> 0) & 0x3f;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
{
return 0x3c;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
{
return 0x3f << 8;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
{
return 0x0;
}
static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
{
return 0x1 << 31;
}
static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
{
return 0x80000000;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
{
return 0x00134124 + i*512;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
{
return (v & 0x3fff) << 0;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
{
return 0x10000;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
{
return 0x100000;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
{
return 0x1000000;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
{
return 0x00134128 + i*512;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
{
return (r >> 0) & 0xfffff;
}
static inline u32 trim_sys_gpcpll_cfg2_r(void)
{
return 0x0013700c;
}
static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
{
return (v & 0xff) << 24;
}
static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
{
return 0xff << 24;
}
static inline u32 trim_sys_gpcpll_cfg3_r(void)
{
return 0x00137018;
}
static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
{
return (v & 0xff) << 16;
}
static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
{
return 0xff << 16;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
{
return 0x0013701c;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
{
return 0x1 << 22;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
{
return 0x400000;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
{
return 0x0;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
{
return 0x1 << 31;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
{
return 0x80000000;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
{
return 0x0;
}
static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
{
return 0x001328a0;
}
static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
{
return (r >> 24) & 0x1;
}
#endif