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gpu: nvgpu: Add magic value at instance block

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This is adding magic value in instance block while
initializing instance block for a context. This will
be verified by FECS firmware.

Bug 3638810

Change-Id: I7d304c1b622b3c9f50a7443e9fadce9bac869258
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2786274
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seeta Rama Raju
2022-12-11 17:06:32 +00:00
committed by mobile promotions
parent a8e38dd72d
commit e0a9553533
6 changed files with 19 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/mm/mm.c
View File

@@ -108,6 +108,10 @@ int nvgpu_alloc_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block)
return err; return err;
} }
if (g->ops.ramin.set_magic_value != NULL) {
g->ops.ramin.set_magic_value(g, inst_block);
}
nvgpu_log_fn(g, "done"); nvgpu_log_fn(g, "done");
return 0; return 0;
} }

3
drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -30,5 +30,6 @@ struct nvgpu_mem;
void ga10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, void ga10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
u64 pdb_addr, struct nvgpu_mem *pdb_mem); u64 pdb_addr, struct nvgpu_mem *pdb_mem);
void ga10b_ramin_set_magic_value(struct gk20a *g, struct nvgpu_mem *inst_block);
#endif /* NVGPU_RAMIN_GA10B_H */ #endif /* NVGPU_RAMIN_GA10B_H */

8
drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -50,3 +50,9 @@ void ga10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
ram_in_page_dir_base_hi_f(pdb_addr_hi)); ram_in_page_dir_base_hi_f(pdb_addr_hi));
} }
void ga10b_ramin_set_magic_value(struct gk20a *g, struct nvgpu_mem *inst_block)
{
nvgpu_mem_wr32(g, inst_block, ram_in_engine_fw_magic_value_w(),
ram_in_engine_fw_magic_value_engine_fw_magic_value_v());
}

1
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -1154,6 +1154,7 @@ static const struct gops_ramin ga10b_ops_ramin = {
.base_shift = gk20a_ramin_base_shift, .base_shift = gk20a_ramin_base_shift,
.alloc_size = gk20a_ramin_alloc_size, .alloc_size = gk20a_ramin_alloc_size,
.set_eng_method_buffer = gv11b_ramin_set_eng_method_buffer, .set_eng_method_buffer = gv11b_ramin_set_eng_method_buffer,
.set_magic_value = ga10b_ramin_set_magic_value,
}; };
static const struct gops_runlist ga10b_ops_runlist = { static const struct gops_runlist ga10b_ops_runlist = {

2
drivers/gpu/nvgpu/include/nvgpu/gops/ramin.h
View File

@@ -214,6 +214,8 @@ struct gops_ramin {
struct nvgpu_mem *inst_block, u64 va_limit); struct nvgpu_mem *inst_block, u64 va_limit);
void (*set_eng_method_buffer)(struct gk20a *g, void (*set_eng_method_buffer)(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 gpu_va); struct nvgpu_mem *inst_block, u64 gpu_va);
void (*set_magic_value)(struct gk20a *g,
struct nvgpu_mem *inst_block);
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
}; };

4
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -72,6 +72,8 @@
#define ram_in_page_dir_base_lo_w() (128U) #define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) ((U32(v) & 0xffffffffU) << 0U) #define ram_in_page_dir_base_hi_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U) #define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_engine_fw_magic_value_w() (131U)
#define ram_in_engine_fw_magic_value_engine_fw_magic_value_v() (0xcafeca11U)
#define ram_in_engine_cs_s() (1U) #define ram_in_engine_cs_s() (1U)
#define ram_in_engine_cs_f(v) ((U32(v) & 0x1U) << 3U) #define ram_in_engine_cs_f(v) ((U32(v) & 0x1U) << 3U)
#define ram_in_engine_cs_m() (U32(0x1U) << 3U) #define ram_in_engine_cs_m() (U32(0x1U) << 3U)