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gpu: nvgpu: Use correct register for ROM control

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We access ROM control register with xve_writel, but we also
add the base register address. This leads to adding the base
address twice, and the access goes to wrong register.

Bug 1846641

Change-Id: I46ef277aac661a08049935b08505120cad1a5e76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1471505
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-04-27 10:48:59 -07:00
committed by mobile promotions
parent 1ffbb2996f
commit e13d0723f6
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/nvgpu/gp106/xve_gp106.c
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@@ -670,13 +670,13 @@ static void xve_rearm_msi_gp106(struct gk20a *g)
static void xve_enable_shadow_rom_gp106(struct gk20a *g)
{
g->ops.xve.xve_writel(g, NV_PCFG + xve_rom_ctrl_r(),
g->ops.xve.xve_writel(g, xve_rom_ctrl_r(),
xve_rom_ctrl_rom_shadow_enabled_f());
}
static void xve_disable_shadow_rom_gp106(struct gk20a *g)
{
g->ops.xve.xve_writel(g, NV_PCFG + xve_rom_ctrl_r(),
g->ops.xve.xve_writel(g, xve_rom_ctrl_r(),
xve_rom_ctrl_rom_shadow_disabled_f());
}