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gpu: nvgpu: add doxygen comments for missing gk20a fields
Many fields of struct gk20a is missing documentation and not all non-safety fields are skipped. Document all safety fields and skip non-safety fields of struct gk20a. Jira NVGPU-6252 Change-Id: I5c280e812f6398c0984db11f9ad144b67a532ab3 Signed-off-by: shashank singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457268 (cherry picked from commit 85d47e3e7f3708f0403ff3810b168862432c29e0) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457263 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
shashank singh
committed by
Alex Waterman
Alex Waterman
parent
b285fb33ee
commit
e13f0db093
@@ -266,6 +266,10 @@ struct gk20a {
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* have had the opportunity to free their private data.
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*/
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void (*gfree)(struct gk20a *g);
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/**
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* Handle to access nvhost APIs.
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*/
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struct nvgpu_nvhost_dev *nvhost;
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/**
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@@ -273,8 +277,10 @@ struct gk20a {
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*/
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unsigned long *enabled_flags;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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/** Used by Linux module to keep track of driver usage */
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nvgpu_atomic_t usage_count;
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/** @endcond */
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/** Used by common.init unit to track users of the driver */
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struct nvgpu_ref refcount;
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@@ -294,21 +300,34 @@ struct gk20a {
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#ifdef CONFIG_PM
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bool suspended;
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#endif
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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bool sw_ready;
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/** @endcond */
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/** Flag to indicate that quiesce framework is initialized. */
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bool sw_quiesce_init_done;
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/** Flag to indicate that system is transitioning to quiesce state. */
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bool sw_quiesce_pending;
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/** Condition variable on which quiesce thread waits. */
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struct nvgpu_cond sw_quiesce_cond;
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/** Quiesce thread id. */
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struct nvgpu_thread sw_quiesce_thread;
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/**
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* Struct having callback and it's arguments. The callback gets called
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* when BUG() is hit by the code.
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*/
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struct nvgpu_bug_cb sw_quiesce_bug_cb;
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/** An entry into list of callbacks to be called when BUG() is hit. */
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struct nvgpu_list_node bug_node;
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/** Controls which messages are logged */
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u64 log_mask;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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u32 log_trace;
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struct nvgpu_mutex tpc_pg_lock;
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/** @endcond */
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/** Stored HW version info */
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struct nvgpu_gpu_params params;
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@@ -325,30 +344,44 @@ struct gk20a {
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struct nvgpu_netlist_vars *netlist_vars;
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bool netlist_valid;
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/** Struct holding the pmu falcon software state. */
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struct nvgpu_falcon pmu_flcn;
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/** Struct holding the fecs falcon software state. */
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struct nvgpu_falcon fecs_flcn;
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/** Struct holding the gpccs falcon software state. */
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struct nvgpu_falcon gpccs_flcn;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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struct nvgpu_falcon nvdec_flcn;
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struct nvgpu_falcon minion_flcn;
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struct nvgpu_falcon gsp_flcn;
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struct clk_gk20a clk;
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/** @endcond */
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/** Top level struct maintaining fifo unit's software state. */
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struct nvgpu_fifo fifo;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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struct nvgpu_nvlink_dev nvlink;
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/** @endcond */
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/** Pointer to struct maintaining GR unit's software state. */
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struct nvgpu_gr *gr;
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u32 num_gr_instances;
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/** Pointer to struct maintaining fbp unit's software state. */
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struct nvgpu_fbp *fbp;
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#ifdef CONFIG_NVGPU_SIM
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struct sim_nvgpu *sim;
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#endif
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struct nvgpu_device_list *devs;
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/** Top level struct maintaining MM unit's software state. */
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struct mm_gk20a mm;
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/** Pointer to struct maintaining PMU unit's software state. */
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struct nvgpu_pmu *pmu;
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/** Pointer to struct maintaining ACR unit's software state. */
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struct nvgpu_acr *acr;
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/** Top level struct maintaining ECC unit's software state. */
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struct nvgpu_ecc ecc;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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struct pmgr_pmupstate *pmgr_pmu;
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struct nvgpu_sec2 sec2;
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/** @endcond */
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#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
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struct nvgpu_sched_ctrl sched_ctrl;
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#endif
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@@ -361,14 +394,24 @@ struct gk20a {
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/** User disabled timeouts */
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bool timeouts_disabled_by_user;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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unsigned int ch_wdt_init_limit_ms;
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/** @endcond */
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/**
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* Timeout after which ctxsw timeout interrupt (if enabled by s/w) will
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* be triggered by h/w if context fails to context switch.
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*/
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u32 ctxsw_timeout_period_ms;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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u32 ctxsw_wdt_period_us;
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struct nvgpu_mutex power_lock;
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/** @endcond */
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/** Lock to protect accessing \a power_on_state. */
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struct nvgpu_spinlock power_spinlock;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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/** Channel priorities */
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u32 tsg_timeslice_low_priority_us;
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u32 tsg_timeslice_medium_priority_us;
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@@ -376,6 +419,7 @@ struct gk20a {
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u32 tsg_timeslice_min_us;
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u32 tsg_timeslice_max_us;
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bool runlist_interleave;
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/** @endcond */
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/** Lock serializing CG an PG programming for various units */
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struct nvgpu_mutex cg_pg_lock;
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@@ -385,21 +429,24 @@ struct gk20a {
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bool blcg_enabled;
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/** ELCG setting read from the platform data */
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bool elcg_enabled;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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bool elpg_enabled;
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bool aelpg_enabled;
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bool can_elpg;
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bool mscg_enabled;
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bool forced_idle;
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bool allow_all;
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/** @endcond */
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/** Ptimer source frequency. */
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u32 ptimer_src_freq;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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int railgate_delay;
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/** @endcond */
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u8 ldiv_slowdown_factor;
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unsigned int aggressive_sync_destroy_thresh;
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bool aggressive_sync_destroy;
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/** @endcond */
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/** Is LS PMU supported? */
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bool support_ls_pmu;
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@@ -407,9 +454,9 @@ struct gk20a {
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/** Is this a virtual GPU? */
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bool is_virtual;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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bool has_cde;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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u32 emc3d_ratio;
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/** @endcond */
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@@ -463,25 +510,32 @@ struct gk20a {
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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/* Called after all references to driver are gone. Unused in safety */
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void (*remove_support)(struct gk20a *g);
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/** @endcond */
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u64 pg_ingating_time_us;
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u64 pg_ungating_time_us;
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u32 pg_gating_cnt;
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/** @endcond */
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/** GPU address-space identifier. */
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struct gk20a_as as;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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struct nvgpu_mutex client_lock;
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int client_refcount; /* open channels and ctrl nodes */
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/** @endcond */
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/** The HAL function pointers */
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struct gpu_ops ops;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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/*used for change of enum zbc update cmd id from ver 0 to ver1*/
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u8 pmu_ver_cmd_id_zbc_table_update;
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/** @endcond */
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/** Top level struct managing interrupt handling. */
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struct nvgpu_mc mc;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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/*
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* The deductible memory size for max_comptag_mem (in MBytes)
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* Usually close to memory size that running system is taking
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@@ -494,7 +548,9 @@ struct gk20a {
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struct nvgpu_cbc *cbc;
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struct nvgpu_ltc *ltc;
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/** @endcond */
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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struct nvgpu_channel_worker {
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struct nvgpu_worker worker;
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@@ -504,15 +560,18 @@ struct gk20a {
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#endif
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} channel_worker;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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struct nvgpu_clk_arb_worker {
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struct nvgpu_worker worker;
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} clk_arb_worker;
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/** @endcond */
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struct {
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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void (*open)(struct nvgpu_channel *ch);
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/** @endcond */
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/** Os specific callback called at channel closure. */
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void (*close)(struct nvgpu_channel *ch, bool force);
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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void (*work_completion_signal)(struct nvgpu_channel *ch);
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void (*work_completion_cancel_sync)(struct nvgpu_channel *ch);
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bool (*os_fence_framework_inst_exists)(struct nvgpu_channel *ch);
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@@ -524,8 +583,11 @@ struct gk20a {
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int (*copy_user_gpfifo)(struct nvgpu_gpfifo_entry *dest,
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struct nvgpu_gpfifo_userdata userdata,
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u32 start, u32 length);
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/** @endcond */
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/** Os specific callback to allocate usermode buffers. */
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int (*alloc_usermode_buffers)(struct nvgpu_channel *c,
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struct nvgpu_setup_bind_args *args);
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/** Os specific callback to free usermode buffers. */
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void (*free_usermode_buffers)(struct nvgpu_channel *c);
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} os_channel;
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@@ -540,10 +602,10 @@ struct gk20a {
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u32 fecs_feature_override_ecc_val;
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#endif
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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u32 tpc_pg_mask;
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bool can_tpc_powergate;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS];
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struct nvgpu_bios *bios;
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@@ -612,6 +674,7 @@ struct gk20a {
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size_t syncpt_unit_size;
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u32 syncpt_size;
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#endif
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/** Full syncpoint aperture. */
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struct nvgpu_mem syncpt_mem;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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