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gpu: nvgpu: update regops ctxsw address types

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Update the below two regops ctxsw address types to fix misnomers:
- CTXSW_ADDR_TYPE_ROP:
  This address type is used to access the PMM config registers and does not
  belong to the ROP unit. Hence, rename it to CTXSW_ADDR_TYPE_PMM_FBPGS_ROP.

- CTXSW_ADDR_TYPE_BE:
  This address type is used to access registers exclusively in ROP unit and not
  the entire BE unit. Hence, its more appropriate to rename it to
  CTXSW_ADDR_TYPE_ROP.

In addition, rename the following functions:
- pri_is_be_addr_shared => pri_is_rop_addr_shared
- pri_be_shared_addr => pri_rop_shared_addr
- pri_is_be_addr => pri_is_rop_addr
- pri_get_be_num => pri_get_rop_num

Bug 3146324

Change-Id: I8613f0972936699b2ef8f7dbe3de78582af2a35f
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2429885
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Antony Clince Alex
2020-10-19 15:46:37 +05:30
committed by Alex Waterman
parent 17d1ecc43c
commit b285fb33ee
3 changed files with 47 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
View File

@@ -191,7 +191,7 @@ bool gk20a_gr_sm_debugger_attached(struct gk20a *g)
/* This function will decode a priv address and return the partition type and numbers. */
int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
enum ctxsw_addr_type *addr_type,
u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *rop_num,
u32 *broadcast_flags)
{
u32 gpc_addr;
@@ -204,7 +204,7 @@ int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
*gpc_num = 0;
*tpc_num = 0;
*ppc_num = 0;
*be_num = 0;
*rop_num = 0;
if (pri_is_gpc_addr(g, addr)) {
*addr_type = CTXSW_ADDR_TYPE_GPC;
@@ -232,13 +232,13 @@ int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
*tpc_num = nvgpu_gr_get_tpc_num(g, gpc_addr);
}
return 0;
} else if (pri_is_be_addr(g, addr)) {
*addr_type = CTXSW_ADDR_TYPE_BE;
if (pri_is_be_addr_shared(g, addr)) {
*broadcast_flags |= PRI_BROADCAST_FLAGS_BE;
} else if (pri_is_rop_addr(g, addr)) {
*addr_type = CTXSW_ADDR_TYPE_ROP;
if (pri_is_rop_addr_shared(g, addr)) {
*broadcast_flags |= PRI_BROADCAST_FLAGS_ROP;
return 0;
}
*be_num = pri_get_be_num(g, addr);
*rop_num = pri_get_rop_num(g, addr);
return 0;
} else if (g->ops.ltc.pri_is_ltc_addr(g, addr)) {
*addr_type = CTXSW_ADDR_TYPE_LTCS;
@@ -313,7 +313,7 @@ int gr_gk20a_create_priv_addr_table(struct gk20a *g,
u32 *num_registers)
{
enum ctxsw_addr_type addr_type;
u32 gpc_num, tpc_num, ppc_num, be_num;
u32 gpc_num, tpc_num, ppc_num, rop_num;
u32 priv_addr, gpc_addr;
u32 broadcast_flags;
u32 t;
@@ -326,7 +326,7 @@ int gr_gk20a_create_priv_addr_table(struct gk20a *g,
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
&gpc_num, &tpc_num, &ppc_num, &be_num,
&gpc_num, &tpc_num, &ppc_num, &rop_num,
&broadcast_flags);
nvgpu_log(g, gpu_dbg_gpu_dbg, "addr_type = %d", addr_type);
if (err != 0) {
@@ -334,13 +334,15 @@ int gr_gk20a_create_priv_addr_table(struct gk20a *g,
}
if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
(addr_type == CTXSW_ADDR_TYPE_BE)) {
/* The BE broadcast registers are included in the compressed PRI
* table. Convert a BE unicast address to a broadcast address
* so that we can look up the offset. */
if ((addr_type == CTXSW_ADDR_TYPE_BE) &&
((broadcast_flags & PRI_BROADCAST_FLAGS_BE) == 0U)) {
priv_addr_table[t++] = pri_be_shared_addr(g, addr);
(addr_type == CTXSW_ADDR_TYPE_ROP)) {
/*
* The ROP broadcast registers are included in the compressed
* PRI table. Convert a ROP unicast address to a broadcast
* address so that we can look up the offset.
*/
if ((addr_type == CTXSW_ADDR_TYPE_ROP) &&
((broadcast_flags & PRI_BROADCAST_FLAGS_ROP) == 0U)) {
priv_addr_table[t++] = pri_rop_shared_addr(g, addr);
} else {
priv_addr_table[t++] = addr;
}
@@ -922,7 +924,7 @@ gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
/* Process the SYS/BE segment. */
if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
(addr_type == CTXSW_ADDR_TYPE_BE)) {
(addr_type == CTXSW_ADDR_TYPE_ROP)) {
list = nvgpu_netlist_get_sys_ctxsw_regs(g);
for (i = 0; i < list->count; i++) {
reg = &list->l[i];
@@ -1146,7 +1148,7 @@ int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
int err;
enum ctxsw_addr_type addr_type;
u32 broadcast_flags;
u32 gpc_num, tpc_num, ppc_num, be_num;
u32 gpc_num, tpc_num, ppc_num, rop_num;
u32 num_gpcs, num_tpcs, num_ppcs;
u32 offset;
u32 sys_priv_offset, gpc_priv_offset;
@@ -1157,7 +1159,7 @@ int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
&gpc_num, &tpc_num, &ppc_num, &be_num,
&gpc_num, &tpc_num, &ppc_num, &rop_num,
&broadcast_flags);
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
"addr_type = %d, broadcast_flags: %08x",
@@ -1197,7 +1199,7 @@ int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
}
if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
(addr_type == CTXSW_ADDR_TYPE_BE) ||
(addr_type == CTXSW_ADDR_TYPE_ROP) ||
(addr_type == CTXSW_ADDR_TYPE_LTS_MAIN)) {
/* Find the offset in the FECS segment. */
offset_to_segment = sys_priv_offset * 256U;

34
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
View File

@@ -1740,7 +1740,7 @@ u32 gv11b_gr_get_egpc_base(struct gk20a *g)
*/
int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
enum ctxsw_addr_type *addr_type,
u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *rop_num,
u32 *broadcast_flags)
{
u32 gpc_addr, tpc_addr;
@@ -1753,7 +1753,7 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
*gpc_num = 0;
*tpc_num = 0;
*ppc_num = 0;
*be_num = 0;
*rop_num = 0;
if (pri_is_gpc_addr(g, addr)) {
*addr_type = CTXSW_ADDR_TYPE_GPC;
@@ -1786,13 +1786,13 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
}
}
return 0;
} else if (pri_is_be_addr(g, addr)) {
*addr_type = CTXSW_ADDR_TYPE_BE;
if (pri_is_be_addr_shared(g, addr)) {
*broadcast_flags |= PRI_BROADCAST_FLAGS_BE;
} else if (pri_is_rop_addr(g, addr)) {
*addr_type = CTXSW_ADDR_TYPE_ROP;
if (pri_is_rop_addr_shared(g, addr)) {
*broadcast_flags |= PRI_BROADCAST_FLAGS_ROP;
return 0;
}
*be_num = pri_get_be_num(g, addr);
*rop_num = pri_get_rop_num(g, addr);
return 0;
} else if (g->ops.ltc.pri_is_ltc_addr(g, addr)) {
*addr_type = CTXSW_ADDR_TYPE_LTCS;
@@ -1834,7 +1834,7 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
} else if (PRI_PMMGS_BASE_ADDR_MASK(addr) == NV_PERF_PMMFBP_FBPGS_ROP) {
*broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP |
PRI_BROADCAST_FLAGS_PMMFBP);
*addr_type = CTXSW_ADDR_TYPE_ROP;
*addr_type = CTXSW_ADDR_TYPE_PMM_FBPGS_ROP;
return 0;
} else if (PRI_PMMS_BASE_ADDR_MASK(addr) == NV_PERF_PMMGPC_GPCS) {
*broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_GPCS |
@@ -1890,7 +1890,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
u32 *num_registers)
{
enum ctxsw_addr_type addr_type;
u32 gpc_num, tpc_num, ppc_num, be_num, sm_num;
u32 gpc_num, tpc_num, ppc_num, rop_num, sm_num;
u32 priv_addr, gpc_addr;
u32 broadcast_flags;
u32 t;
@@ -1902,7 +1902,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
&gpc_num, &tpc_num, &ppc_num, &be_num,
&gpc_num, &tpc_num, &ppc_num, &rop_num,
&broadcast_flags);
nvgpu_log(g, gpu_dbg_gpu_dbg, "addr_type = %d", addr_type);
if (err != 0) {
@@ -1910,15 +1910,15 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
}
if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
(addr_type == CTXSW_ADDR_TYPE_BE)) {
(addr_type == CTXSW_ADDR_TYPE_ROP)) {
/*
* The BE broadcast registers are included in the compressed PRI
* table. Convert a BE unicast address to a broadcast address
* The ROP broadcast registers are included in the compressed PRI
* table. Convert a ROP unicast address to a broadcast address
* so that we can look up the offset
*/
if ((addr_type == CTXSW_ADDR_TYPE_BE) &&
(broadcast_flags & PRI_BROADCAST_FLAGS_BE) == 0U) {
priv_addr_table[t++] = pri_be_shared_addr(g, addr);
if ((addr_type == CTXSW_ADDR_TYPE_ROP) &&
(broadcast_flags & PRI_BROADCAST_FLAGS_ROP) == 0U) {
priv_addr_table[t++] = pri_rop_shared_addr(g, addr);
} else {
priv_addr_table[t++] = addr;
}
@@ -2043,7 +2043,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
priv_addr_table, &t,
nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START),
nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT));
} else if ((addr_type == CTXSW_ADDR_TYPE_ROP) &&
} else if ((addr_type == CTXSW_ADDR_TYPE_PMM_FBPGS_ROP) &&
((broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP) != 0U)) {
gr_gv11b_split_pmm_fbp_broadcast_address(g,
PRI_PMMGS_OFFSET_MASK(addr),

16
drivers/gpu/nvgpu/hal/gr/gr/gr_pri_gk20a.h
View File

@@ -173,28 +173,28 @@ static inline u32 pri_becs_addr_mask(u32 addr)
{
return addr & (BIT32(pri_becs_addr_width()) - 1U);
}
static inline bool pri_is_be_addr_shared(struct gk20a *g, u32 addr)
static inline bool pri_is_rop_addr_shared(struct gk20a *g, u32 addr)
{
u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_SHARED_BASE);
u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE);
return (addr >= rop_shared_base) &&
(addr < rop_shared_base + rop_stride);
}
static inline u32 pri_be_shared_addr(struct gk20a *g, u32 addr)
static inline u32 pri_rop_shared_addr(struct gk20a *g, u32 addr)
{
u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_SHARED_BASE);
return rop_shared_base + pri_becs_addr_mask(addr);
}
static inline bool pri_is_be_addr(struct gk20a *g, u32 addr)
static inline bool pri_is_rop_addr(struct gk20a *g, u32 addr)
{
u32 rop_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_BASE);
u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE);
return ((addr >= rop_base) &&
(addr < rop_base + nvgpu_ltc_get_ltc_count(g) * rop_stride)) ||
pri_is_be_addr_shared(g, addr);
pri_is_rop_addr_shared(g, addr);
}
static inline u32 pri_get_be_num(struct gk20a *g, u32 addr)
static inline u32 pri_get_rop_num(struct gk20a *g, u32 addr)
{
u32 i, start;
u32 num_fbps = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPS);
@@ -234,13 +234,13 @@ enum ctxsw_addr_type {
CTXSW_ADDR_TYPE_SYS = 0,
CTXSW_ADDR_TYPE_GPC = 1,
CTXSW_ADDR_TYPE_TPC = 2,
CTXSW_ADDR_TYPE_BE = 3,
CTXSW_ADDR_TYPE_ROP = 3,
CTXSW_ADDR_TYPE_PPC = 4,
CTXSW_ADDR_TYPE_LTCS = 5,
CTXSW_ADDR_TYPE_FBPA = 6,
CTXSW_ADDR_TYPE_EGPC = 7,
CTXSW_ADDR_TYPE_ETPC = 8,
CTXSW_ADDR_TYPE_ROP = 9,
CTXSW_ADDR_TYPE_PMM_FBPGS_ROP = 9,
CTXSW_ADDR_TYPE_FBP = 10,
CTXSW_ADDR_TYPE_LTS_MAIN = 11,
};
@@ -248,7 +248,7 @@ enum ctxsw_addr_type {
#define PRI_BROADCAST_FLAGS_NONE 0U
#define PRI_BROADCAST_FLAGS_GPC BIT32(0)
#define PRI_BROADCAST_FLAGS_TPC BIT32(1)
#define PRI_BROADCAST_FLAGS_BE BIT32(2)
#define PRI_BROADCAST_FLAGS_ROP BIT32(2)
#define PRI_BROADCAST_FLAGS_PPC BIT32(3)
#define PRI_BROADCAST_FLAGS_LTCS BIT32(4)
#define PRI_BROADCAST_FLAGS_LTSS BIT32(5)