nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 11:04:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: enable HWPM Mode-E context switch

Browse Source 
- Write new pm mode to context buffer header. Ucode use
this mode to enable mode-e context switch. This is Mode-B
context switch of PMs with Mode-E streamout on one context.
If this mode is set, Ucode makes sure that Mode-E pipe
(perfmons, routers, pma) is idle before it context switches PMs.
- This allows us to collect counters in a secure way
(i.e. on context basis) with stream out.

Bug 2106999

Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760366
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vaibhav Kachore
2018-07-06 15:10:03 +05:30
committed by mobile promotions
parent 4cd59404a2
commit e14fdcd8f1
13 changed files with 120 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
View File

@@ -1039,12 +1039,33 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
return err;
}
/*
* Convert linux hwpm ctxsw mode type of the form of NVGPU_DBG_GPU_HWPM_CTXSW_MODE_*
* into common hwpm ctxsw mode type of the form of NVGPU_DBG_HWPM_CTXSW_MODE_*
*/
static u32 nvgpu_hwpm_ctxsw_mode_to_common_mode(u32 mode)
{
switch (mode){
case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW:
return NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW;
case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW:
return NVGPU_DBG_HWPM_CTXSW_MODE_CTXSW;
case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW:
return NVGPU_DBG_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW;
}
return mode;
}
static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args)
{
int err;
struct gk20a *g = dbg_s->g;
struct channel_gk20a *ch_gk20a;
u32 mode = nvgpu_hwpm_ctxsw_mode_to_common_mode(args->mode);
nvgpu_log_fn(g, "%s pm ctxsw mode = %d", g->name, args->mode);
@@ -1080,7 +1101,8 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
goto clean_up;
}
err = g->ops.gr.update_hwpm_ctxsw_mode(g, ch_gk20a, 0,
args->mode == NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW);
mode);
if (err)
nvgpu_err(g,
"error (%d) during pm ctxsw mode update", err);