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gpu: nvgpu: falcon code cleanup

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-Created common falcon function nvgpu_flcn_bl_bootstrap() to
 bootstrap falcon bootloader

-Created HAL gk20a_falcon_bl_bootstrap() which does actual
 bootloader bootstrap by fetching parameters and loading
 code/parameters as needed.

-Created HAL ops bl_bootstrap under nvgpu_falcon_ops.

-Created struct nvgpu_falcon_bl_info to hold info required
 for bootloader to pass to common function

-Removed falcons bootstrap code in multiple file & made
 changes to fill struct nvgpu_falcon_bl_info & call
 nvgpu_flcn_bl_bootstrap().

Change-Id: Iee275233915ff11f9afb5207ac0c3338ca9dacc1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756104
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2018-06-21 00:12:01 +05:30
committed by mobile promotions
parent 876953fbb8
commit 4cd59404a2
6 changed files with 93 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -357,6 +357,24 @@ void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn)
flcn->flcn_id);
}
int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn,
struct nvgpu_falcon_bl_info *bl_info)
{
struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
int status = 0;
if (flcn_ops->bl_bootstrap != NULL) {
status = flcn_ops->bl_bootstrap(flcn, bl_info);
}
else {
nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
flcn->flcn_id);
status = -EINVAL;
}
return status;
}
void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id)
{
struct nvgpu_falcon *flcn = NULL;

41
drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
View File

@@ -432,6 +432,46 @@ static void gk20a_falcon_mailbox_write(struct nvgpu_falcon *flcn,
nvgpu_err(g, "incorrect mailbox id %d", mailbox_index);
}
static int gk20a_falcon_bl_bootstrap(struct nvgpu_falcon *flcn,
struct nvgpu_falcon_bl_info *bl_info)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 virt_addr = 0;
u32 dst = 0;
int err = 0;
/*copy bootloader interface structure to dmem*/
err = gk20a_flcn_copy_to_dmem(flcn, 0, (u8 *)bl_info->bl_desc,
bl_info->bl_desc_size, (u8)0);
if (err != 0) {
goto exit;
}
/* copy bootloader to TOP of IMEM */
dst = (falcon_falcon_hwcfg_imem_size_v(gk20a_readl(g,
base_addr + falcon_falcon_hwcfg_r())) << 8) - bl_info->bl_size;
err = gk20a_flcn_copy_to_imem(flcn, dst, (u8 *)(bl_info->bl_src),
bl_info->bl_size, (u8)0, false, bl_info->bl_start_tag);
if (err != 0) {
goto exit;
}
gk20a_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, 0xDEADA5A5U);
virt_addr = bl_info->bl_start_tag << 8;
err = gk20a_falcon_bootstrap(flcn, virt_addr);
exit:
if (err != 0) {
nvgpu_err(g, "falcon id-0x%x bootstrap failed", flcn->flcn_id);
}
return err;
}
static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
@@ -644,6 +684,7 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn)
flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats;
flcn_ops->mailbox_read = gk20a_falcon_mailbox_read;
flcn_ops->mailbox_write = gk20a_falcon_mailbox_write;
flcn_ops->bl_bootstrap = gk20a_falcon_bl_bootstrap;
gk20a_falcon_engine_dependency_ops(flcn);
}

28
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -1165,11 +1165,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu,
struct flcn_bl_dmem_desc *pbl_desc, u32 bl_sz)
{
struct gk20a *g = gk20a_from_pmu(pmu);
struct acr_desc *acr = &g->acr;
struct mm_gk20a *mm = &g->mm;
u32 virt_addr = 0;
struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc;
u32 dst;
struct nvgpu_falcon_bl_info bl_info;
nvgpu_log_fn(g, " ");
gk20a_writel(g, pwr_falcon_itfen_r(),
@@ -1181,23 +1178,12 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu,
pwr_pmu_new_instblk_valid_f(1) |
pwr_pmu_new_instblk_target_sys_coh_f());
/*copy bootloader interface structure to dmem*/
nvgpu_flcn_copy_to_dmem(pmu->flcn, 0, (u8 *)pbl_desc,
sizeof(struct flcn_bl_dmem_desc), 0);
/* copy bootloader to TOP of IMEM */
dst = (pwr_falcon_hwcfg_imem_size_v(
gk20a_readl(g, pwr_falcon_hwcfg_r())) << 8) - bl_sz;
nvgpu_flcn_copy_to_imem(pmu->flcn, dst,
(u8 *)(acr->hsbl_ucode.cpu_va), bl_sz, 0, 0,
pmu_bl_gm10x_desc->bl_start_tag);
gm20b_dbg_pmu(g, "Before starting falcon with BL\n");
virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
nvgpu_flcn_bootstrap(pmu->flcn, virt_addr);
bl_info.bl_src = g->acr.hsbl_ucode.cpu_va;
bl_info.bl_desc = (u8 *)pbl_desc;
bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc);
bl_info.bl_size = bl_sz;
bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag;
nvgpu_flcn_bl_bootstrap(&g->pmu_flcn, &bl_info);
return 0;
}

30
drivers/gpu/nvgpu/gp106/sec2_gp106.c
View File

@@ -82,12 +82,9 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
void *desc, u32 bl_sz)
{
struct gk20a *g = gk20a_from_pmu(pmu);
struct acr_desc *acr = &g->acr;
struct mm_gk20a *mm = &g->mm;
u32 virt_addr = 0;
struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc;
struct nvgpu_falcon_bl_info bl_info;
u32 data = 0;
u32 dst;
nvgpu_log_fn(g, " ");
@@ -113,25 +110,12 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
data |= (1 << 3);
gk20a_writel(g, psec_falcon_engctl_r(), data);
/*copy bootloader interface structure to dmem*/
nvgpu_flcn_copy_to_dmem(&g->sec2_flcn, 0, (u8 *)desc,
sizeof(struct flcn_bl_dmem_desc), 0);
/* copy bootloader to TOP of IMEM */
dst = (psec_falcon_hwcfg_imem_size_v(
gk20a_readl(g, psec_falcon_hwcfg_r())) << 8) - bl_sz;
nvgpu_flcn_copy_to_imem(&g->sec2_flcn, dst,
(u8 *)(acr->hsbl_ucode.cpu_va), bl_sz, 0, 0,
pmu_bl_gm10x_desc->bl_start_tag);
gm20b_dbg_pmu(g, "Before starting falcon with BL\n");
gk20a_writel(g, psec_falcon_mailbox0_r(), 0xDEADA5A5);
virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
nvgpu_flcn_bootstrap(&g->sec2_flcn, virt_addr);
bl_info.bl_src = g->acr.hsbl_ucode.cpu_va;
bl_info.bl_desc = desc;
bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
bl_info.bl_size = bl_sz;
bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag;
nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, &bl_info);
return 0;
}

28
drivers/gpu/nvgpu/gv11b/acr_gv11b.c
View File

@@ -206,11 +206,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu,
struct flcn_bl_dmem_desc_v1 *pbl_desc, u32 bl_sz)
{
struct gk20a *g = gk20a_from_pmu(pmu);
struct acr_desc *acr = &g->acr;
struct mm_gk20a *mm = &g->mm;
u32 virt_addr = 0;
struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc;
u32 dst;
struct nvgpu_falcon_bl_info bl_info;
nvgpu_log_fn(g, " ");
@@ -225,23 +222,12 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu,
pwr_pmu_new_instblk_target_sys_coh_f() :
pwr_pmu_new_instblk_target_sys_ncoh_f())) ;
/*copy bootloader interface structure to dmem*/
nvgpu_flcn_copy_to_dmem(pmu->flcn, 0, (u8 *)pbl_desc,
sizeof(struct flcn_bl_dmem_desc_v1), 0);
/* copy bootloader to TOP of IMEM */
dst = (pwr_falcon_hwcfg_imem_size_v(
gk20a_readl(g, pwr_falcon_hwcfg_r())) << 8) - bl_sz;
nvgpu_flcn_copy_to_imem(pmu->flcn, dst,
(u8 *)(acr->hsbl_ucode.cpu_va), bl_sz, 0, 0,
pmu_bl_gm10x_desc->bl_start_tag);
gv11b_dbg_pmu(g, "Before starting falcon with BL\n");
virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
nvgpu_flcn_bootstrap(pmu->flcn, virt_addr);
bl_info.bl_src = g->acr.hsbl_ucode.cpu_va;
bl_info.bl_desc = (u8 *)pbl_desc;
bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
bl_info.bl_size = bl_sz;
bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag;
nvgpu_flcn_bl_bootstrap(&g->pmu_flcn, &bl_info);
return 0;
}

14
drivers/gpu/nvgpu/include/nvgpu/falcon.h
View File

@@ -165,6 +165,7 @@ struct nvgpu_falcon_dma_info {
struct gk20a;
struct nvgpu_falcon;
struct nvgpu_falcon_bl_info;
struct nvgpu_falcon_version_ops {
void (*start_cpu_secure)(struct nvgpu_falcon *flcn);
@@ -198,6 +199,16 @@ struct nvgpu_falcon_ops {
u32 data);
int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector);
void (*dump_falcon_stats)(struct nvgpu_falcon *flcn);
int (*bl_bootstrap)(struct nvgpu_falcon *flcn,
struct nvgpu_falcon_bl_info *bl_info);
};
struct nvgpu_falcon_bl_info {
void *bl_src;
u8 *bl_desc;
u32 bl_desc_size;
u32 bl_size;
u32 bl_start_tag;
};
struct nvgpu_falcon {
@@ -245,8 +256,9 @@ int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size);
void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size);
void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn);
int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn,
struct nvgpu_falcon_bl_info *bl_info);
void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id);
#endif /* __FALCON_H__ */