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Revert "Revert "gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl""

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This patch was reverted as the "set_sm_exception_type_mask" HAL
assignment for gp10b was missing causing regression on Pascal platform.

Added missing gp10b HAL assignment for setting SM exception mask.

Bug 200447406
This reverts commit ce5228e094.

Change-Id: Ic48f4661fd4b6100310f8b4d23d902847e31f5df
Signed-off-by: aalex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837653
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
aalex
2018-09-21 23:02:41 +05:30
committed by Abdul Salam
parent 4758f98679
commit e1a4bc8401
15 changed files with 81 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
View File

@@ -154,10 +154,6 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s);
static int gk20a_dbg_gpu_do_dev_open(struct inode *inode,
struct file *filp, bool is_profiler);
static int nvgpu_set_sm_exception_type_mask_locked(
struct dbg_session_gk20a *dbg_s,
u32 exception_mask);
unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait)
{
unsigned int mask = 0;
@@ -1807,44 +1803,13 @@ out:
return err;
}
static int nvgpu_set_sm_exception_type_mask_locked(
struct dbg_session_gk20a *dbg_s,
u32 exception_mask)
{
struct gk20a *g = dbg_s->g;
int err = 0;
struct channel_gk20a *ch = NULL;
/*
* Obtain the fisrt channel from the channel list in
* dbg_session, find the context associated with channel
* and set the sm_mask_type to that context
*/
ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
if (ch != NULL) {
struct tsg_gk20a *tsg;
tsg = tsg_gk20a_from_ch(ch);
if (tsg != NULL) {
tsg->sm_exception_mask_type = exception_mask;
goto type_mask_end;
}
}
nvgpu_log_fn(g, "unable to find the TSG\n");
err = -EINVAL;
type_mask_end:
return err;
}
static int nvgpu_dbg_gpu_set_sm_exception_type_mask(
struct dbg_session_gk20a *dbg_s,
static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args)
{
int err = 0;
struct gk20a *g = dbg_s->g;
u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE;
struct channel_gk20a *ch = NULL;
switch (args->exception_type_mask) {
case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL:
@@ -1865,10 +1830,17 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask(
return err;
}
nvgpu_mutex_acquire(&g->dbg_sessions_lock);
err = nvgpu_set_sm_exception_type_mask_locked(dbg_s,
sm_exception_mask_type);
nvgpu_mutex_release(&g->dbg_sessions_lock);
ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
if (ch != NULL) {
if (g->ops.fifo.set_sm_exception_type_mask == NULL) {
nvgpu_err(g, "set_sm_exception_type_mask not set");
return -EINVAL;
}
err = g->ops.fifo.set_sm_exception_type_mask(ch,
sm_exception_mask_type);
} else {
err = -EINVAL;
}
return err;
}