gpu: nvgpu: ga10x: compute gnic_stride

GNIC register stride calculation is fixed by adding new hal to compute
the stride by getting the difference of gpc1 and gpc0 xbar_gnic strides
for ga10x GPUs.

Bug 200782045

Change-Id: Iaa84109bd9f1a974ef1af6fee136ca1fcc89bbb1
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2624848
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

arch/nvgpu-gpu_hw.yaml

@@ -259,6 +259,7 @@ headers:
              include/nvgpu/hw/ga100/hw_xp_ga100.h,
              include/nvgpu/hw/ga100/hw_xve_ga100.h,
              include/nvgpu/hw/ga100/hw_fbpa_ga100.h,
+             include/nvgpu/hw/ga100/hw_xbar_ga100.h,
              include/nvgpu/hw/ga10b/hw_bus_ga10b.h,
              include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h,
              include/nvgpu/hw/ga10b/hw_ce_ga10b.h,
@@ -290,4 +291,5 @@ headers:
              include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h,
              include/nvgpu/hw/ga10b/hw_therm_ga10b.h,
              include/nvgpu/hw/ga10b/hw_timer_ga10b.h,
-             include/nvgpu/hw/ga10b/hw_top_ga10b.h ]
+             include/nvgpu/hw/ga10b/hw_top_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_xbar_ga10b.h ]

drivers/gpu/nvgpu/common/gr/hwpm_map.c

@@ -286,7 +286,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 			return -EINVAL;
 		}
 
-		base = NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE * gpc_num;
+		base = (g->ops.gr.ctxsw_prog.hw_get_pm_gpc_gnic_stride(g)) * gpc_num;
 		if (add_ctxsw_buffer_map_entries(map,
 				nvgpu_netlist_get_pm_ucgpc_ctxsw_regs(g),
 				count, offset, max_cnt, base, ~U32(0U)) != 0) {

drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
 #include <nvgpu/nvgpu_mem.h>
 
 #include <nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h>
+#include <nvgpu/hw/ga100/hw_xbar_ga100.h>
 
 #ifdef CONFIG_DEBUG_FS
 void ga100_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g,
@@ -82,3 +83,10 @@ void ga100_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g,
 			ctxsw_prog_main_image_compute_preemption_options_o()));
 }
 #endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+u32 ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride(struct gk20a *g)
+{
+	return (xbar_mxbar_pri_gpc1_gnic0_preg_pm_ctrl_r() -
+			xbar_mxbar_pri_gpc0_gnic0_preg_pm_ctrl_r());
+}
+#endif

drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -34,6 +34,7 @@ u32 ga100_ctxsw_prog_hw_get_fecs_header_size(void);
 u32 ga100_ctxsw_prog_hw_get_gpccs_header_size(void);
 bool ga100_ctxsw_prog_check_main_image_header_magic(u32 *context);
 bool ga100_ctxsw_prog_check_local_header_magic(u32 *context);
+u32 ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride(struct gk20a *g);
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_DEBUG_FS
 void ga100_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g,

drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h

@@ -58,6 +58,9 @@ void gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw(struct gk20a *g,
 bool gm20b_ctxsw_prog_is_zcull_mode_separate_buffer(u32 mode);
 #endif /* CONFIG_NVGPU_GRAPHICS */
 #ifdef CONFIG_NVGPU_DEBUGGER
+
+#define  NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE 0x20U
+
 u32 gm20b_ctxsw_prog_hw_get_gpccs_header_size(void);
 u32 gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes(void);
 u32 gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes(void);
@@ -83,6 +86,7 @@ void gm20b_ctxsw_prog_get_extended_buffer_size_offset(u32 *context,
 	u32 *size, u32 *offset);
 void gm20b_ctxsw_prog_get_ppc_info(u32 *context, u32 *num_ppcs, u32 *ppc_mask);
 u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context);
+u32 gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride(struct gk20a *g);
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_NVGPU_FECS_TRACE
 u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void);

drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -167,4 +167,9 @@ u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context)
 	u32 data = *(context + (ctxsw_prog_local_priv_register_ctl_o() >> 2));
 	return ctxsw_prog_local_priv_register_ctl_offset_v(data);
 }
+
+u32 gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride(struct gk20a *g)
+{
+	return  NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE;
+}
 #endif /* CONFIG_NVGPU_DEBUGGER */

drivers/gpu/nvgpu/hal/init/hal_ga100.c

@@ -492,6 +492,7 @@ static const struct gops_gr_ctxsw_prog ga100_ops_gr_ctxsw_prog = {
 	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
 	.set_pmu_options_boost_clock_frequencies = NULL,
 	.hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride,
+	.hw_get_pm_gpc_gnic_stride = ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_DEBUG_FS
 	.dump_ctxsw_stats = ga100_ctxsw_prog_dump_ctxsw_stats,

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -200,6 +200,7 @@
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_ga100.h"
 #ifdef CONFIG_NVGPU_DEBUGGER
 #include "hal/gr/gr/gr_gk20a.h"
 #include "hal/gr/gr/gr_gm20b.h"
@@ -459,6 +460,7 @@ static const struct gops_gr_ctxsw_prog ga10b_ops_gr_ctxsw_prog = {
 	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
 	.set_pmu_options_boost_clock_frequencies = NULL,
 	.hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride,
+	.hw_get_pm_gpc_gnic_stride = ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride,
 	.hw_get_main_header_size = ga10b_ctxsw_prog_hw_get_main_header_size,
 	.hw_get_gpccs_header_stride = ga10b_ctxsw_prog_hw_get_gpccs_header_stride,
 	.get_compute_sysreglist_offset = ga10b_ctxsw_prog_get_compute_sysreglist_offset,

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -234,6 +234,7 @@ static const struct gops_gr_ctxsw_prog gm20b_ops_gr_ctxsw_prog = {
 	.get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset,
 	.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
 	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
+	.hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_NVGPU_FECS_TRACE
 	.hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -297,6 +297,7 @@ static const struct gops_gr_ctxsw_prog gp10b_ops_gr_ctxsw_prog = {
 	.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
 	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
 	.set_pmu_options_boost_clock_frequencies = gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies,
+	.hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_DEBUG_FS
 	.dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -379,6 +379,7 @@ static const struct gops_gr_ctxsw_prog gv11b_ops_gr_ctxsw_prog = {
 	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
 	.set_pmu_options_boost_clock_frequencies = NULL,
 	.hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride,
+	.hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_DEBUG_FS
 	.dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -423,6 +423,7 @@ static const struct gops_gr_ctxsw_prog tu104_ops_gr_ctxsw_prog = {
 	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
 	.set_pmu_options_boost_clock_frequencies = gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies,
 	.hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride,
+	.hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_DEBUG_FS
 	.dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats,

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c

@@ -54,6 +54,7 @@
 #include "hal/fifo/usermode_tu104.h"
 #include "hal/fifo/usermode_ga10b.h"
 #include "hal/fifo/fifo_intr_gv11b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_ga100.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h"
 #include "hal/gr/gr/gr_ga10b.h"
 #include "hal/gr/init/gr_init_ga10b.h"
@@ -321,6 +322,7 @@ static const struct gops_gr_ctxsw_prog vgpu_ga10b_ops_gr_ctxsw_prog = {
 	.get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset,
 	.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
 	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
+	.hw_get_pm_gpc_gnic_stride = ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_NVGPU_FECS_TRACE
 	.hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -292,6 +292,7 @@ static const struct gops_gr_ctxsw_prog vgpu_gv11b_ops_gr_ctxsw_prog = {
 	.get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset,
 	.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
 	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
+	.hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_NVGPU_FECS_TRACE
 	.hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,

drivers/gpu/nvgpu/include/nvgpu/gops/gr.h

@@ -1014,7 +1014,8 @@ struct gops_gr_ctxsw_prog {
 					struct gk20a *g,
 					struct nvgpu_mem *ctx_mem,
 					u32 boosted_ctx);
-#endif
+	u32 (*hw_get_pm_gpc_gnic_stride)(struct gk20a *g);
+#endif /* CONFIG_NVGPU_DEBUGGER */
 #ifdef CONFIG_DEBUG_FS
 	void (*dump_ctxsw_stats)(struct gk20a *g,
 				 struct nvgpu_mem *ctx_mem);

drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xbar_ga100.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_XBAR_GA100_H
+#define NVGPU_HW_XBAR_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define xbar_mxbar_pri_gpc0_gnic0_preg_pm_ctrl_r()                 (0x0013cc14U)
+#define xbar_mxbar_pri_gpc1_gnic0_preg_pm_ctrl_r()                 (0x0013cc94U)
+#endif

drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_xbar_ga10b.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_XBAR_GA10B_H
+#define NVGPU_HW_XBAR_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define xbar_mxbar_pri_gpc0_gnic0_preg_pm_ctrl_r()                 (0x0013cc14U)
+#define xbar_mxbar_pri_gpc1_gnic0_preg_pm_ctrl_r()                 (0x0013cc94U)
+#endif