gpu: nvgpu: add hal.gr.init hal to get max subctx count

Add new HAL API g->ops.gr.init.get_max_subctx_count() in hal.gr.init
unit that returns max subctx count defined by h/w

Use this new hal in all GR code instead of using value stored in struct
fifo_gk20a

Jira NVGPU-2961

Change-Id: I5db1d827c3b7581a5ba7aca4314ba2f5a590d80c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2097532
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gv100/gr_gv100.c

@@ -46,7 +46,6 @@ void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 u32 gr_gv100_get_patch_slots(struct gk20a *g)
 {
 	struct gr_gk20a *gr = &g->gr;
-	struct fifo_gk20a *f = &g->fifo;
 	u32 size = 0;
 
 	/*
@@ -69,7 +68,7 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g)
 	/*
 	 * We need this for all subcontexts
 	 */
-	size *= f->max_subctx_count;
+	size *= g->ops.gr.init.get_max_subctx_count();
 
 	/*
 	 * Add space for a partition mode change as well

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -694,6 +694,8 @@ static const struct gpu_ops gv100_ops = {
 				gv11b_gr_init_commit_cbes_reserve,
 			.gfxp_wfi_timeout =
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
+			.get_max_subctx_count =
+				gv11b_gr_init_get_max_subctx_count,
 		},
 		.intr = {
 			.set_shader_exceptions =

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -60,7 +60,6 @@
 #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
 
 #include "fifo_gv11b.h"
 #include "gr_gv11b.h"
@@ -944,7 +943,7 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g)
 {
 	struct fifo_gk20a *f = &g->fifo;
 
-	f->max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v();
+	f->max_subctx_count = g->ops.gr.init.get_max_subctx_count();
 
 	/* configure userd writeback timer */
 	nvgpu_writel(g, fifo_userd_writeback_r(),

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -670,6 +670,8 @@ static const struct gpu_ops gv11b_ops = {
 				gv11b_gr_init_commit_cbes_reserve,
 			.gfxp_wfi_timeout =
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
+			.get_max_subctx_count =
+				gv11b_gr_init_get_max_subctx_count,
 		},
 		.intr = {
 			.set_shader_exceptions =

drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c

@@ -782,8 +782,7 @@ static int gv11b_gr_init_write_bundle_veid_state(struct gk20a *g, u32 index,
 	u32  num_subctx;
 	int err = 0;
 
-	/* TODO: get this value through FIFO hal */
-	num_subctx = g->fifo.max_subctx_count;
+	num_subctx = g->ops.gr.init.get_max_subctx_count();
 
 	for (j = 0U; j < num_subctx; j++) {
 		nvgpu_log_fn(g, "write bundle_address_r for subctx: %d", j);
@@ -891,3 +890,8 @@ void gv11b_gr_init_commit_gfxp_wfi_timeout(struct gk20a *g,
 	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_fe_gfxp_wfi_timeout_r(),
 		timeout, patch);
 }
+
+u32 gv11b_gr_init_get_max_subctx_count(void)
+{
+	return gr_pri_fe_chip_def_info_max_veid_count_init_v();
+}

drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h

@@ -78,4 +78,6 @@ void gv11b_gr_init_commit_cbes_reserve(struct gk20a *g,
 void gv11b_gr_init_commit_gfxp_wfi_timeout(struct gk20a *g,
 	struct nvgpu_gr_ctx *gr_ctx, u32 timeout, bool patch);
 
+u32 gv11b_gr_init_get_max_subctx_count(void);
+
 #endif /* NVGPU_GR_INIT_GV11B_H */

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -787,6 +787,7 @@ struct gpu_ops {
 			void (*gfxp_wfi_timeout)(struct gk20a *g,
 				struct nvgpu_gr_ctx *gr_ctx, u32 timeout,
 				bool patch);
+			u32 (*get_max_subctx_count)(void);
 		} init;
 
 		struct {

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -727,6 +727,8 @@ static const struct gpu_ops tu104_ops = {
 				gv11b_gr_init_commit_cbes_reserve,
 			.gfxp_wfi_timeout =
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
+			.get_max_subctx_count =
+				gv11b_gr_init_get_max_subctx_count,
 		},
 		.intr = {
 			.set_shader_exceptions =