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gpu: nvgpu: tu104: remove smpc extended buffer workaround

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In Turing, SMPC gets fe2all_freeze, so extended buffer workaround
is not needed. This workaround has been removed from Ucode, but
not from kernel, this causes smpc counters to either not start or
not stop in some cases.

Bug 2420353

Change-Id: Idb0ddbc4488031b78678adeccb6d77d1b28e0c70
Signed-off-by: akgoel <akgoel@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1931362
(cherry picked from commit 00d813d0a04ce77a18801a1adf8733a52ba769f0)
Reviewed-on: https://git-master.nvidia.com/r/1932436
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Akash Goel
2018-10-20 11:39:48 -05:00
committed by mobile promotions
parent f8ce19f879
commit e3653e7b5e
3 changed files with 21 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/nvgpu/tu104/gr_tu104.c
View File

@@ -489,3 +489,18 @@ int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr,
fail: fail:
return -EINVAL; return -EINVAL;
} }
void gr_tu104_init_sm_dsm_reg_info(void)
{
return;
}
void gr_tu104_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
u32 *num_sm_dsm_perf_ctrl_regs,
u32 **sm_dsm_perf_ctrl_regs,
u32 *ctrl_register_stride)
{
*num_sm_dsm_perf_ctrl_regs = 0;
*sm_dsm_perf_ctrl_regs = NULL;
*ctrl_register_stride = 0;
}

4
drivers/gpu/nvgpu/tu104/gr_tu104.h
View File

@@ -88,4 +88,8 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr, int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data); u32 class_num, u32 offset, u32 data);
void gr_tu104_init_sm_dsm_reg_info(void);
void gr_tu104_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
u32 *num_sm_dsm_perf_ctrl_regs, u32 **sm_dsm_perf_ctrl_regs,
u32 *ctrl_register_stride);
#endif #endif

4
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -362,7 +362,7 @@ static const struct gpu_ops tu104_ops = {
.is_valid_gfx_class = gr_tu104_is_valid_gfx_class, .is_valid_gfx_class = gr_tu104_is_valid_gfx_class,
.is_valid_compute_class = gr_tu104_is_valid_compute_class, .is_valid_compute_class = gr_tu104_is_valid_compute_class,
.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, .get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = gr_gv11b_init_fs_state, .init_fs_state = gr_gv11b_init_fs_state,
.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
@@ -399,7 +399,7 @@ static const struct gpu_ops tu104_ops = {
.get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
.get_max_fbps_count = gr_gm20b_get_max_fbps_count, .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .init_sm_dsm_reg_info = gr_tu104_init_sm_dsm_reg_info,
.wait_empty = gr_gv11b_wait_empty, .wait_empty = gr_gv11b_wait_empty,
.init_cyclestats = gr_gm20b_init_cyclestats, .init_cyclestats = gr_gm20b_init_cyclestats,
.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,