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gpu: nvgpu: perf: Refactor Perf unit

Browse Source 
-Renamed and moved nvgpu_pmu_perf struct from public
to unit specific
-Renamed all functions as per public/private format

NVGPU-5029

Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300609
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2020-02-21 15:28:47 +05:30
committed by Alex Waterman
parent 14f268563a
commit e424e4791a
18 changed files with 123 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/clk_arb/clk_arb.c
View File

@@ -118,7 +118,7 @@ int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
u16 clk_cur;
u32 num_points;
struct clk_set_info *p0_info;
struct nvgpu_pmu_perf_pstate_clk_info *p0_info;
table = NV_READ_ONCE(arb->current_vf_table);
/* make flag visible when all data has resolved in the tables */

4
drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c
View File

@@ -57,7 +57,7 @@ int gv100_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
u16 *min_mhz, u16 *max_mhz)
{
u32 clkwhich;
struct clk_set_info *p0_info;
struct nvgpu_pmu_perf_pstate_clk_info *p0_info;
struct nvgpu_avfsfllobjs *pfllobjs = g->pmu->clk_pmu->avfs_fllobjs;
u16 limit_min_mhz;
u16 gpcclk_cap_mhz;
@@ -111,7 +111,7 @@ int gv100_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
u16 *default_mhz)
{
u32 clkwhich;
struct clk_set_info *p0_info;
struct nvgpu_pmu_perf_pstate_clk_info *p0_info;
bool error_status = false;
u16 gpcclk_cap_mhz;

4
drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
View File

@@ -1472,10 +1472,10 @@ done:
static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain,
u32 *gpcclk_clkmhz,
struct nvgpu_clk_slave_freq *vf_point,
struct ctrl_perf_change_seq_change_input *change_input)
struct nvgpu_pmu_perf_change_input_clk_info *change_input)
{
struct nvgpu_clk_domain *pclk_domain;
struct clk_set_info *p0_info;
struct nvgpu_pmu_perf_pstate_clk_info *p0_info;
u32 max_clkmhz;
u16 max_ratio;
u8 i = 0;

21
drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
View File

@@ -106,7 +106,7 @@ static void build_change_seq_boot (struct gk20a *g)
struct change_seq_pmu *perf_change_seq_pmu =
&(g->pmu->perf_pmu->changeseq_pmu);
struct nvgpu_clk_domain *pdomain;
struct clk_set_info *p0_info;
struct nvgpu_pmu_perf_pstate_clk_info *p0_info;
struct change_seq_pmu_script *script_last =
&perf_change_seq_pmu->script_last;
u8 i = 0;
@@ -155,7 +155,7 @@ static void build_change_seq_boot (struct gk20a *g)
/* Assume everything is P0 - Need to find the index for P0 */
script_last->buf.change.data.pstate_index =
nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0);
perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);
nvgpu_mem_wr_n(g, nvgpu_pmu_super_surface_mem(g,
pmu, pmu->super_surface),
@@ -234,7 +234,7 @@ int perf_change_seq_pmu_setup(struct gk20a *g)
/* Assume everything is P0 - Need to find the index for P0 */
perf_change_seq_pmu->script_last.buf.change.data.pstate_index =
nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0);;
perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);;
nvgpu_mem_wr_n(g, nvgpu_pmu_super_surface_mem(g,
pmu, pmu->super_surface),
@@ -272,10 +272,10 @@ int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g,
sizeof(struct ctrl_perf_change_seq_change_input));
g->pmu->clk_pmu->set_p0_clks(g, &gpcclk_domain, &gpcclk_clkmhz,
vf_point, &change_input);
vf_point, &change_input.clk);
change_input.pstate_index =
nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0);
perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);
change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE;
change_input.vf_points_cache_counter = 0xFFFFFFFFU;
@@ -320,7 +320,7 @@ int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g,
sizeof(struct nv_pmu_rpc_perf_change_seq_queue_change));
rpc.change = change_input;
rpc.change.pstate_index =
nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0);
perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);
change_seq_pmu->change_state = 0U;
change_seq_pmu->start_time = nvgpu_current_time_us();
PMU_RPC_EXECUTE_CPB(status, pmu, PERF,
@@ -343,3 +343,12 @@ int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g,
change_seq_pmu->stop_time = nvgpu_current_time_us();
return status;
}
void nvgpu_perf_change_seq_execute_time(struct gk20a *g, s64 *change_time)
{
struct change_seq_pmu *change_seq_pmu =
&g->pmu->perf_pmu->changeseq_pmu;
s64 diff = change_seq_pmu->stop_time - change_seq_pmu->start_time;
*change_time = diff;
}

35
drivers/gpu/nvgpu/common/pmu/perf/change_seq.h
View File

@@ -25,10 +25,45 @@
#ifndef NVGPU_CHANGE_SEQ_H
#define NVGPU_CHANGE_SEQ_H
#include "ucode_perf_change_seq_inf.h"
#define SEQ_SCRIPT_CURR 0x0U
#define SEQ_SCRIPT_LAST 0x1U
#define SEQ_SCRIPT_QUERY 0x2U
struct change_seq_pmu_script {
struct perf_change_seq_pmu_script buf;
u32 super_surface_offset;
};
struct change_seq {
u8 version;
bool b_enabled_pmu_support;
u32 thread_seq_id_last;
u64 thread_carry_over_timens;
struct ctrl_perf_change_seq_change last_pstate_values;
struct boardobjgrpmask_e32 clk_domains_exclusion_mask;
struct boardobjgrpmask_e32 clk_domains_inclusion_mask;
u32 client_lock_mask;
};
struct change_seq_pmu {
struct change_seq super;
bool b_lock;
bool b_vf_point_check_ignore;
u32 cpu_adverised_step_id_mask;
u32 cpu_step_id_mask;
u32 event_mask_pending;
u32 event_mask_received;
u32 last_completed_change_Seq_id;
struct change_seq_pmu_script script_curr;
struct change_seq_pmu_script script_last;
struct change_seq_pmu_script script_query;
u32 change_state;
s64 start_time;
s64 stop_time;
};
int perf_change_seq_sw_setup(struct gk20a *g);
int perf_change_seq_pmu_setup(struct gk20a *g);

12
drivers/gpu/nvgpu/common/pmu/perf/perf.c
View File

@@ -32,17 +32,13 @@
#include "ucode_perf_change_seq_inf.h"
#include "ucode_perf_pstate_inf.h"
#include "ucode_perf_vfe_inf.h"
#include "vfe_equ.h"
#include "vfe_var.h"
#include "change_seq.h"
#include "pstate.h"
#include "perf.h"
static int pmu_set_boot_clk_runcb_fn(void *arg)
{
struct gk20a *g = (struct gk20a *)arg;
struct perf_pmupstate *perf_pmu = g->pmu->perf_pmu;
struct nvgpu_vfe_invalidate *vfe_init = &perf_pmu->vfe_init;
struct nvgpu_pmu_perf *perf_pmu = g->pmu->perf_pmu;
struct perf_vfe_invalidate *vfe_init = &perf_pmu->vfe_init;
nvgpu_log_fn(g, "thread start");
@@ -65,7 +61,7 @@ static int tu104_pmu_handle_perf_event(struct gk20a *g, void *pmumsg)
{
struct pmu_nvgpu_rpc_perf_event *msg =
(struct pmu_nvgpu_rpc_perf_event *)pmumsg;
struct perf_pmupstate *perf_pmu = g->pmu->perf_pmu;
struct nvgpu_pmu_perf *perf_pmu = g->pmu->perf_pmu;
struct change_seq_pmu *change_pmu = &g->pmu->perf_pmu->changeseq_pmu;
nvgpu_log_fn(g, " ");
@@ -90,7 +86,7 @@ static int tu104_pmu_handle_perf_event(struct gk20a *g, void *pmumsg)
static int perf_pmu_init_vfe_perf_event(struct gk20a *g)
{
struct perf_pmupstate *perf_pmu = g->pmu->perf_pmu;
struct nvgpu_pmu_perf *perf_pmu = g->pmu->perf_pmu;
char thread_name[64];
int err = 0;

19
drivers/gpu/nvgpu/common/pmu/perf/perf.h
View File

@@ -25,6 +25,11 @@
#ifndef PMU_PERF_H_
#define PMU_PERF_H_
#include "vfe_equ.h"
#include "vfe_var.h"
#include "change_seq.h"
#include "pstate.h"
/* PERF RPC ID Definitions */
#define NV_PMU_RPC_ID_PERF_VFE_CALLBACK 0x01U
#define NV_PMU_RPC_ID_PERF_SEQ_COMPLETION 0x02U
@@ -52,6 +57,18 @@ struct pmu_nvgpu_rpc_perf_event {
struct pmu_nvgpu_rpc_header rpc_hdr;
};
int nvgpu_get_pstate_entry_idx(struct gk20a *g, u32 num);
struct perf_vfe_invalidate {
bool state_change;
struct nvgpu_cond wq;
struct nvgpu_thread state_task;
};
struct nvgpu_pmu_perf {
struct vfe_vars vfe_varobjs;
struct vfe_equs vfe_equobjs;
struct pstates pstatesobjs;
struct perf_vfe_invalidate vfe_init;
struct change_seq_pmu changeseq_pmu;
};
#endif /* PMU_PERF_H_ */

12
drivers/gpu/nvgpu/common/pmu/perf/pstate.c
View File

@@ -37,7 +37,7 @@
#include "pstate.h"
#include "perf.h"
int nvgpu_get_pstate_entry_idx(struct gk20a *g, u32 num)
int perf_pstate_get_table_entry_idx(struct gk20a *g, u32 num)
{
struct pstates *pstates = &(g->pmu->perf_pmu->pstatesobjs);
struct pstate *pstate;
@@ -206,7 +206,7 @@ static int parse_pstate_entry_6x(struct gk20a *g,
pstate->pcie_idx = entry->pcie_idx;
for (clkidx = 0; clkidx < hdr->clock_entry_count; clkidx++) {
struct clk_set_info *pclksetinfo;
struct nvgpu_pmu_perf_pstate_clk_info *pclksetinfo;
struct vbios_pstate_entry_clock_6x *clk_entry;
domain = 0;
@@ -336,7 +336,7 @@ static int perf_pstate_pmudatainit(struct gk20a *g,
pset->numClkDomains = pprogs->num_clk_domains;
pset->boot_pstate_idx =
nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0);
perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);
done:
return status;
@@ -435,11 +435,11 @@ static struct pstate *perf_pstate_find(struct gk20a *g, u32 num)
return NULL;
}
struct clk_set_info *nvgpu_pmu_perf_pstate_get_clk_set_info(struct gk20a *g,
u32 pstate_num, u32 clkwhich)
struct nvgpu_pmu_perf_pstate_clk_info *nvgpu_pmu_perf_pstate_get_clk_set_info(
struct gk20a *g, u32 pstate_num, u32 clkwhich)
{
struct pstate *pstate = perf_pstate_find(g, pstate_num);
struct clk_set_info *info;
struct nvgpu_pmu_perf_pstate_clk_info *info;
u32 clkidx;
if (pstate == NULL) {

12
drivers/gpu/nvgpu/common/pmu/perf/pstate.h
View File

@@ -27,9 +27,14 @@
#define CTRL_PERF_PSTATE_TYPE_35 0x05U
struct clk_set_info_list {
struct pstate_clk_info_list {
u32 num_info;
struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
struct nvgpu_pmu_perf_pstate_clk_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
};
struct pstates {
struct boardobjgrp_e32 super;
u8 num_clk_domains;
};
struct pstate {
@@ -39,10 +44,11 @@ struct pstate {
u32 flags;
u8 pcie_idx;
u8 nvlink_idx;
struct clk_set_info_list clklist;
struct pstate_clk_info_list clklist;
};
int perf_pstate_sw_setup(struct gk20a *g);
int perf_pstate_pmu_setup(struct gk20a *g);
int perf_pstate_get_table_entry_idx(struct gk20a *g, u32 num);
#endif /* NVGPU_PERF_PSTATE_H */

4
drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h
View File

@@ -80,9 +80,7 @@ struct ctrl_perf_change_seq_change_input {
u32 pstate_index;
u32 flags;
u32 vf_points_cache_counter;
struct ctrl_boardobjgrp_mask_e32 clk_domains_mask;
struct ctrl_perf_chage_seq_input_clk
clk[CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS];
struct nvgpu_pmu_perf_change_input_clk_info clk;
struct ctrl_boardobjgrp_mask_e32 volt_rails_mask;
struct ctrl_perf_chage_seq_input_volt
volt[CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS];

1
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
View File

@@ -35,6 +35,7 @@
#include "ucode_perf_vfe_inf.h"
#include "vfe_equ.h"
#include "vfe_var.h"
#include "perf.h"
static int vfe_equ_node_depending_mask_combine(struct gk20a *g,
struct boardobjgrp *pboardobjgrp, u8 equ_idx,

8
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.h
View File

@@ -24,6 +24,12 @@
#ifndef NVGPU_PERF_VFE_EQU_H
#define NVGPU_PERF_VFE_EQU_H
#include "ucode_perf_vfe_inf.h"
struct vfe_equs {
struct boardobjgrp_e255 super;
};
struct vfe_equ {
struct boardobj super;
u8 var_idx;
@@ -56,7 +62,7 @@ struct vfe_equ_minmax {
struct vfe_equ_quadratic {
struct vfe_equ super;
u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT];
u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT];
};
struct vfe_equ_scalar {

1
drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c
View File

@@ -31,6 +31,7 @@
#include "ucode_perf_vfe_inf.h"
#include "vfe_var.h"
#include "perf.h"
static int vfe_vars_pmudatainit(struct gk20a *g,
struct boardobjgrp *pboardobjgrp,

5
drivers/gpu/nvgpu/common/pmu/perf/vfe_var.h
View File

@@ -23,6 +23,11 @@
#ifndef NVGPU_PERF_VFE_VAR_H
#define NVGPU_PERF_VFE_VAR_H
struct vfe_vars {
struct boardobjgrp_e32 super;
u8 polling_periodms;
};
struct vfe_var {
struct boardobj super;
u32 out_range_min;

5
drivers/gpu/nvgpu/hal/clk/clk_tu104.c
View File

@@ -571,10 +571,7 @@ unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain)
void tu104_get_change_seq_time(struct gk20a *g, s64 *change_time)
{
struct change_seq_pmu *change_seq_pmu = &g->pmu->perf_pmu->changeseq_pmu;
s64 diff = change_seq_pmu->stop_time - change_seq_pmu->start_time;
*change_time = diff;
nvgpu_perf_change_seq_execute_time(g, change_time);
}
#endif
void tu104_change_host_clk_source(struct gk20a *g)

2
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -303,7 +303,7 @@ struct nvgpu_pmu {
struct nvgpu_pmu_perfmon *pmu_perfmon;
struct nvgpu_clk_pmupstate *clk_pmu;
struct therm_pmupstate *therm_pmu;
struct perf_pmupstate *perf_pmu;
struct nvgpu_pmu_perf *perf_pmu;
struct nvgpu_pmu_volt *volt;
void (*remove_support)(struct nvgpu_pmu *pmu);

4
drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
View File

@@ -133,7 +133,7 @@ struct nvgpu_clk_progs;
struct nvgpu_clk_vf_points;
struct nvgpu_clk_mclk_state;
struct nvgpu_clk_slave_freq;
struct ctrl_perf_change_seq_change_input;
struct nvgpu_pmu_perf_change_input_clk_info;
struct nvgpu_vin_device;
struct nvgpu_clk_domain;
struct nvgpu_clk_arb;
@@ -259,7 +259,7 @@ struct nvgpu_clk_pmupstate {
int (*get_fll)(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk);
void (*set_p0_clks)(struct gk20a *g, u8 *gpcclk_domain,
u32 *gpcclk_clkmhz, struct nvgpu_clk_slave_freq *vf_point,
struct ctrl_perf_change_seq_change_input *change_input);
struct nvgpu_pmu_perf_change_input_clk_info *change_input);
struct nvgpu_clk_domain *(*clk_get_clk_domain)
(struct nvgpu_clk_pmupstate *pclk, u8 idx);
int (*clk_domain_clk_prog_link)(struct gk20a *g,

76
drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h
View File

@@ -25,9 +25,7 @@
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/boardobjgrpmask.h>
/* Dependency of this include will be removed in further CL */
#include "../../../common/pmu/perf/ucode_perf_change_seq_inf.h"
#include <nvgpu/pmu/clk/clk.h>
struct nvgpu_clk_slave_freq;
@@ -64,72 +62,21 @@ struct nvgpu_clk_slave_freq;
#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004U)
#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006U)
struct nvgpu_vfe_invalidate {
bool state_change;
struct nvgpu_cond wq;
struct nvgpu_thread state_task;
};
struct vfe_vars {
struct boardobjgrp_e32 super;
u8 polling_periodms;
};
struct vfe_equs {
struct boardobjgrp_e255 super;
};
struct change_seq_pmu_script {
struct perf_change_seq_pmu_script buf;
u32 super_surface_offset;
};
struct clk_set_info {
struct nvgpu_pmu_perf_pstate_clk_info {
u32 clkwhich;
u32 nominal_mhz;
u16 min_mhz;
u16 max_mhz;
};
struct pstates {
struct boardobjgrp_e32 super;
u8 num_clk_domains;
struct perf_chage_seq_input_clk {
u32 clk_freq_khz;
};
struct change_seq {
u8 version;
bool b_enabled_pmu_support;
u32 thread_seq_id_last;
u64 thread_carry_over_timens;
struct ctrl_perf_change_seq_change last_pstate_values;
struct boardobjgrpmask_e32 clk_domains_exclusion_mask;
struct boardobjgrpmask_e32 clk_domains_inclusion_mask;
u32 client_lock_mask;
};
struct change_seq_pmu {
struct change_seq super;
bool b_lock;
bool b_vf_point_check_ignore;
u32 cpu_adverised_step_id_mask;
u32 cpu_step_id_mask;
u32 event_mask_pending;
u32 event_mask_received;
u32 last_completed_change_Seq_id;
struct change_seq_pmu_script script_curr;
struct change_seq_pmu_script script_last;
struct change_seq_pmu_script script_query;
u32 change_state;
s64 start_time;
s64 stop_time;
};
struct perf_pmupstate {
struct vfe_vars vfe_varobjs;
struct vfe_equs vfe_equobjs;
struct pstates pstatesobjs;
struct nvgpu_vfe_invalidate vfe_init;
struct change_seq_pmu changeseq_pmu;
struct nvgpu_pmu_perf_change_input_clk_info {
struct ctrl_boardobjgrp_mask_e32 clk_domains_mask;
struct perf_chage_seq_input_clk
clk[CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS];
};
int nvgpu_pmu_perf_init(struct gk20a *g);
@@ -147,8 +94,9 @@ int nvgpu_pmu_perf_vfe_get_freq_margin(struct gk20a *g, u32 *fmargin_mhz);
int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g,
struct nvgpu_clk_slave_freq *vf_point);
struct clk_set_info *nvgpu_pmu_perf_pstate_get_clk_set_info(struct gk20a *g,
u32 pstate_num,
u32 clkwhich);
struct nvgpu_pmu_perf_pstate_clk_info *nvgpu_pmu_perf_pstate_get_clk_set_info(
struct gk20a *g, u32 pstate_num, u32 clkwhich);
void nvgpu_perf_change_seq_execute_time(struct gk20a *g, s64 *change_time);
#endif /* NVGPU_PMU_PERF_H */