gpu: nvgpu: fix MISRA Rule 8.6 violations

ifdef function prototypes with CONFIG_* defines. This fixes MISRA rule
8.6 violations which complain about undefined functions.
Also moved nvgpu_channel_get_from_file prototype to ioctl_channel.h &
nvgpu_probe to driver_common.h as those are linux specific. Define
nvgpu_init_soc_vars in posix/soc.c as it is implemented in QNX.

JIRA NVGPU-3873

Change-Id: I5d2b238e1b5d1318867cd2416ac5f03cc6ab7c6a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196794
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/class/class_gm20b.h

@@ -26,7 +26,10 @@
 #include <nvgpu/types.h>
 
 bool gm20b_class_is_valid(u32 class_num);
+
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 bool gm20b_class_is_valid_gfx(u32 class_num);
 bool gm20b_class_is_valid_compute(u32 class_num);
+#endif
 
 #endif /* NVGPU_CLASS_GM20B */

drivers/gpu/nvgpu/hal/fb/fb_gm20b.h

@@ -32,8 +32,10 @@ struct nvgpu_mem;
 
 void gm20b_fb_init_hw(struct gk20a *g);
 int gm20b_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void fb_gm20b_init_fs_state(struct gk20a *g);
 void gm20b_fb_set_mmu_page_size(struct gk20a *g);
+#endif
 u32 gm20b_fb_mmu_ctrl(struct gk20a *g);
 u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g);
 u32 gm20b_fb_mmu_debug_wr(struct gk20a *g);

drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.h

@@ -25,6 +25,9 @@
 struct gk20a;
 
 u64 gp10b_determine_L2_size_bytes(struct gk20a *g);
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void gp10b_ltc_init_fs_state(struct gk20a *g);
-void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled);
+#endif
+void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled);
+
 #endif

drivers/gpu/nvgpu/hal/top/top_gm20b.h

@@ -33,13 +33,16 @@ struct nvgpu_device_info;
 int gm20b_device_info_parse_enum(struct gk20a *g, u32 table_entry,
 					u32 *engine_id, u32 *runlist_id,
 					u32 *intr_id, u32 *reset_id);
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 int gm20b_device_info_parse_data(struct gk20a *g, u32 table_entry, u32 *inst_id,
 					u32 *pri_base, u32 *fault_id);
 int gm20b_get_device_info(struct gk20a *g, struct nvgpu_device_info *dev_info,
 					u32 engine_type, u32 inst_id);
-bool gm20b_is_engine_gr(struct gk20a *g, u32 engine_type);
 bool gm20b_is_engine_ce(struct gk20a *g, u32 engine_type);
 u32 gm20b_get_ce_inst_id(struct gk20a *g, u32 engine_type);
+#endif
+
+bool gm20b_is_engine_gr(struct gk20a *g, u32 engine_type);
 
 u32 gm20b_top_get_max_gpc_count(struct gk20a *g);
 u32 gm20b_top_get_max_tpc_per_gpc_count(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/ce.h

@@ -71,6 +71,7 @@ enum {
 
 int nvgpu_ce_init_support(struct gk20a *g);
 
+#ifdef CONFIG_NVGPU_DGPU
 /* global CE app related apis */
 int nvgpu_ce_app_init_support(struct gk20a *g);
 void nvgpu_ce_app_suspend(struct gk20a *g);
@@ -93,5 +94,5 @@ int nvgpu_ce_execute_ops(struct gk20a *g,
 		u32 request_operation,
 		u32 submit_flags,
 		struct nvgpu_fence_type **fence_out);
-
+#endif
 #endif /*NVGPU_CE_H*/

drivers/gpu/nvgpu/include/nvgpu/channel.h

@@ -617,7 +617,6 @@ void nvgpu_channel_update_priv_cmd_q_and_free_entry(
 	struct nvgpu_channel *ch, struct priv_cmd_entry *e);
 int nvgpu_channel_worker_init(struct gk20a *g);
 void nvgpu_channel_worker_deinit(struct gk20a *g);
-struct nvgpu_channel *nvgpu_channel_get_from_file(int fd);
 void nvgpu_channel_update(struct nvgpu_channel *c);
 int nvgpu_channel_alloc_job(struct nvgpu_channel *c,
 		struct nvgpu_channel_job **job_out);

drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h

@@ -23,14 +23,6 @@
 #ifndef NVGPU_COMMON_H
 #define NVGPU_COMMON_H
 
-struct gk20a;
-struct class;
-
-int nvgpu_probe(struct gk20a *g,
-		const char *debugfs_symlink,
-		const char *interface_name,
-		struct class *device_class);
-
 void nvgpu_kernel_restart(void *cmd);
 
 #endif

drivers/gpu/nvgpu/include/nvgpu/posix/io.h

@@ -92,8 +92,6 @@ void nvgpu_posix_io_reset_error_code(struct gk20a *g);
 
 /* allocate and register reg_space */
 int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size);
-int nvgpu_posix_io_add_reg_space_ext(struct gk20a *g, u32 base, u32 size,
-	u32 *data);
 struct nvgpu_posix_io_reg_space *nvgpu_posix_io_get_reg_space(struct gk20a *g,
 	u32 addr);
 void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base);

drivers/gpu/nvgpu/os/linux/driver_common.h

@@ -17,6 +17,14 @@
 #ifndef NVGPU_LINUX_DRIVER_COMMON
 #define NVGPU_LINUX_DRIVER_COMMON
 
+struct gk20a;
+struct class;
+
+int nvgpu_probe(struct gk20a *g,
+		const char *debugfs_symlink,
+		const char *interface_name,
+		struct class *device_class);
+
 void nvgpu_init_gk20a(struct gk20a *g);
 
 #endif

drivers/gpu/nvgpu/os/linux/ioctl_as.c

@@ -33,6 +33,7 @@
 
 #include "platform_gk20a.h"
 #include "ioctl_as.h"
+#include "ioctl_channel.h"
 #include "os_linux.h"
 
 static u32 gk20a_as_translate_as_alloc_space_flags(struct gk20a *g, u32 flags)

drivers/gpu/nvgpu/os/linux/ioctl_channel.h

@@ -21,6 +21,7 @@ struct inode;
 struct file;
 struct gk20a;
 struct nvgpu_channel_open_args;
+struct nvgpu_channel;
 
 struct gk20a_cs_snapshot_client_linux {
 	struct gk20a_cs_snapshot_client cs_client;
@@ -29,6 +30,8 @@ struct gk20a_cs_snapshot_client_linux {
 	struct dma_buf		*dma_handler;
 };
 
+struct nvgpu_channel *nvgpu_channel_get_from_file(int fd);
+
 int gk20a_channel_open(struct inode *inode, struct file *filp);
 int gk20a_channel_release(struct inode *inode, struct file *filp);
 long gk20a_channel_ioctl(struct file *filp,

drivers/gpu/nvgpu/os/linux/module.h

@@ -17,6 +17,7 @@ struct gk20a;
 struct device;
 struct platform_device;
 struct nvgpu_os_linux;
+struct class;
 
 int gk20a_pm_finalize_poweron(struct device *dev);
 int nvgpu_finalize_poweron_linux(struct nvgpu_os_linux *l);

drivers/gpu/nvgpu/os/posix/soc.c

@@ -66,3 +66,8 @@ u64 nvgpu_get_cycles(void)
 {
 	return (u64)nvgpu_current_time_us();
 }
+
+int nvgpu_init_soc_vars(struct gk20a *g)
+{
+	return 0;
+}