gpu: nvgpu: gsp: add priv lockdown release check

- NVGPU need to check for priv lockdown release before configuring
  any priv registers. In current GSP bootstrap sequence has irq
  configuration after GSP engine reset which is causing priv errors.
  So irq configuration should be done after GSP firmware releases
  priv lockdown.
- Removed clearing irq mask and dest registers before configuring
  them as GSP firmware would have done partial irq configuration
  before releasing the priv.

NVGPU-7342

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I4b6e83452c051654253e02bfb72330b3d6aec3fd
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2649826
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.c

@@ -214,6 +214,30 @@ int nvgpu_gsp_wait_for_mailbox_update(struct nvgpu_gsp *gsp,
 	return 0;
 }
 
+int nvgpu_gsp_wait_for_priv_lockdown_release(struct nvgpu_gsp *gsp,
+		signed int timeoutms)
+{
+	struct nvgpu_falcon *flcn = gsp->gsp_flcn;
+
+	nvgpu_log_fn(gsp->g, " ");
+
+	do {
+		if (!gsp->g->ops.falcon.is_priv_lockdown(flcn)) {
+			break;
+		}
+
+		if (timeoutms <= 0) {
+			nvgpu_err(gsp->g, "gsp priv lockdown release timedout");
+			return -1;
+		}
+
+		nvgpu_msleep(10);
+		timeoutms -= 10;
+	} while (true);
+
+	return 0;
+}
+
 int nvgpu_gsp_bootstrap_ns(struct gk20a *g, struct nvgpu_gsp *gsp)
 {
 	int err = 0;

drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c

@@ -170,6 +170,13 @@ int nvgpu_gsp_sched_bootstrap_ns(struct gk20a *g)
 		goto de_init;
 	}
 
+	status = nvgpu_gsp_wait_for_priv_lockdown_release(gsp_sched->gsp,
+				GSP_WAIT_TIME_MS);
+	if (status != 0) {
+		nvgpu_err(g, "gsp PRIV lockdown release wait failed ");
+		goto de_init;
+	}
+
 	return status;
 de_init:
 	nvgpu_gsp_sched_sw_deinit(g);

drivers/gpu/nvgpu/include/nvgpu/gsp.h

@@ -63,4 +63,6 @@ int nvgpu_gsp_wait_for_mailbox_update(struct nvgpu_gsp *gsp,
 int nvgpu_gsp_bootstrap_ns(struct gk20a *g, struct nvgpu_gsp *gsp);
 void nvgpu_gsp_isr(struct gk20a *g);
 void nvgpu_gsp_isr_support(struct gk20a *g, struct nvgpu_gsp *gsp, bool enable);
+int nvgpu_gsp_wait_for_priv_lockdown_release(struct nvgpu_gsp *gsp,
+		signed int timeoutms);
 #endif /* NVGPU_GSP */