mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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- NVGPU need to check for priv lockdown release before configuring any priv registers. In current GSP bootstrap sequence has irq configuration after GSP engine reset which is causing priv errors. So irq configuration should be done after GSP firmware releases priv lockdown. - Removed clearing irq mask and dest registers before configuring them as GSP firmware would have done partial irq configuration before releasing the priv. NVGPU-7342 Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com> Change-Id: I4b6e83452c051654253e02bfb72330b3d6aec3fd Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2649826 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
192 lines
4.7 KiB
C
192 lines
4.7 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/string.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/log.h>
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#include <nvgpu/errno.h>
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#include <nvgpu/gsp.h>
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#include <nvgpu/gsp_sched.h>
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#include "gsp_scheduler.h"
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#include "ipc/gsp_seq.h"
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#include "ipc/gsp_queue.h"
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static void gsp_sched_get_file_names(struct gk20a *g, struct gsp_fw *gsp_ucode)
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{
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nvgpu_log_fn(g, " ");
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gsp_ucode->code_name = GSP_DBG_RISCV_FW_CODE;
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gsp_ucode->data_name = GSP_DBG_RISCV_FW_DATA;
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gsp_ucode->manifest_name = GSP_DBG_RISCV_FW_MANIFEST;
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}
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void nvgpu_gsp_sched_suspend(struct gk20a *g, struct nvgpu_gsp_sched *gsp_sched)
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{
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struct nvgpu_gsp *gsp = gsp_sched->gsp;
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nvgpu_log_fn(g, " ");
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if (gsp == NULL) {
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nvgpu_info(g, "GSP not initialized");
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return;
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}
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gsp_sched->gsp_ready = false;
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nvgpu_gsp_suspend(g, gsp);
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}
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static void gsp_sched_deinit(struct gk20a *g, struct nvgpu_gsp_sched *gsp_sched)
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{
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gsp_sched->gsp_ready = false;
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nvgpu_kfree(g, gsp_sched);
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gsp_sched = NULL;
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}
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void nvgpu_gsp_sched_sw_deinit(struct gk20a *g)
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{
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struct nvgpu_gsp_sched *gsp_sched = g->gsp_sched;
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nvgpu_log_fn(g, " ");
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if (gsp_sched == NULL) {
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return;
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}
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if (gsp_sched->gsp != NULL) {
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nvgpu_gsp_sw_deinit(g, gsp_sched->gsp);
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}
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if (gsp_sched->sequences != NULL) {
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nvgpu_gsp_sequences_free(g, gsp_sched->sequences);
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}
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if (gsp_sched->queues != NULL) {
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nvgpu_gsp_queues_free(g, gsp_sched->queues);
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}
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if (gsp_sched != NULL) {
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gsp_sched_deinit(g, gsp_sched);
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}
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}
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int nvgpu_gsp_sched_sw_init(struct gk20a *g)
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{
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int err = 0;
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struct nvgpu_gsp_sched *gsp_sched;
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struct nvgpu_gsp *gsp;
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nvgpu_log_fn(g, " ");
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if (g->gsp_sched != NULL) {
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/*
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* Recovery/unrailgate case, we do not need to do gsp_sched init as
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* gsp_sched is set during cold boot & doesn't execute gsp_sched clean
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* up as part of power off sequence, so reuse to perform faster boot.
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*/
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return err;
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}
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/* Init struct holding the gsp sched software state */
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g->gsp_sched = (struct nvgpu_gsp_sched *)
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nvgpu_kzalloc(g, sizeof(struct nvgpu_gsp_sched));
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if (g->gsp_sched == NULL) {
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err = -ENOMEM;
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goto de_init;
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}
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/* Init struct holding the gsp software state */
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g->gsp_sched->gsp = (struct nvgpu_gsp *)
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nvgpu_kzalloc(g, sizeof(struct nvgpu_gsp));
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if (g->gsp_sched->gsp == NULL) {
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err = -ENOMEM;
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goto de_init;
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}
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gsp_sched = g->gsp_sched;
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gsp = g->gsp_sched->gsp;
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/* gsp falcon software state */
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gsp->gsp_flcn = &g->gsp_flcn;
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gsp->g = g;
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/* Init isr mutex */
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nvgpu_mutex_init(&gsp->isr_mutex);
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err = nvgpu_gsp_sequences_init(g, gsp_sched);
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if (err != 0) {
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nvgpu_err(g, "GSP sequences init failed");
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goto de_init;
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}
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nvgpu_log_fn(g, " Done ");
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return err;
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de_init:
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nvgpu_gsp_sched_sw_deinit(g);
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return err;
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}
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int nvgpu_gsp_sched_bootstrap_ns(struct gk20a *g)
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{
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struct nvgpu_gsp_sched *gsp_sched = g->gsp_sched;
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int status = 0;
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#ifdef CONFIG_NVGPU_FALCON_DEBUG
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status = nvgpu_gsp_debug_buf_init(g, GSP_SCHED_DEBUG_BUFFER_QUEUE,
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GSP_SCHED_DMESG_BUFFER_SIZE);
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if (status != 0) {
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nvgpu_err(g, "GSP sched debug buf init failed");
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goto de_init;
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}
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#endif
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/* Get ucode file names */
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gsp_sched_get_file_names(g, &gsp_sched->gsp->gsp_ucode);
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status = nvgpu_gsp_bootstrap_ns(g, gsp_sched->gsp);
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if (status != 0) {
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nvgpu_err(g, " GSP sched bootstrap failed ");
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goto de_init;
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}
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status = nvgpu_gsp_wait_for_priv_lockdown_release(gsp_sched->gsp,
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GSP_WAIT_TIME_MS);
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if (status != 0) {
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nvgpu_err(g, "gsp PRIV lockdown release wait failed ");
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goto de_init;
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}
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return status;
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de_init:
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nvgpu_gsp_sched_sw_deinit(g);
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return status;
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}
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void nvgpu_gsp_sched_isr(struct gk20a *g)
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{
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struct nvgpu_gsp *gsp = g->gsp_sched->gsp;
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g->ops.gsp.gsp_isr(g, gsp);
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}
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