- NVGPU need to check for priv lockdown release before configuring
any priv registers. In current GSP bootstrap sequence has irq
configuration after GSP engine reset which is causing priv errors.
So irq configuration should be done after GSP firmware releases
priv lockdown.
- Removed clearing irq mask and dest registers before configuring
them as GSP firmware would have done partial irq configuration
before releasing the priv.
NVGPU-7342
Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I4b6e83452c051654253e02bfb72330b3d6aec3fd
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2649826
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Separated gsp unit into three unit:
- GSP unit which holds the core functionality of GSP RISCV core,
bootstrap, interrupt, etc.
- GSP Scheduler to hold the cmd/msg management, IPC, etc.
- GSP Test to hold stress test ucode specific support.
NVGPU-7492
Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I12340dc776d610502f28c8574843afc7481c0871
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2660619
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
