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gpu: nvgpu: Move HS Falcon ucode bootstrap to Falcon unit

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Moving HS ucode bootstrap from ACR unit to Falcon unit as HS ucode
bootstrap needs to be accessed by multiple units. Currently FB unit
calls ACR unit function to do self HS load & bootstrap memory unlock
HS ucode. This adds dependency on ACR unit which is not correct. So,
moving to Falcon unit to make it generic.

JIRA NVGPU-3811

Change-Id: I3696296c9df661d821199cb93872265ef6d10bfc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195016
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-09-11 11:55:41 +05:30
committed by Alex Waterman
parent 7d8757b9a4
commit e77a911568
3 changed files with 92 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

57
drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
View File

@@ -187,16 +187,8 @@ int nvgpu_acr_self_hs_load_bootstrap(struct gk20a *g, struct nvgpu_falcon *flcn,
struct acr_fw_header *fw_hdr = NULL;
u32 *ucode_header = NULL;
u32 *ucode = NULL;
u32 sec_imem_dest = 0U;
int err = 0;
/* falcon reset */
err = nvgpu_falcon_reset(flcn);
if (err != 0) {
nvgpu_err(g, "nvgpu_falcon_reset() failed err=%d", err);
return err;
}
hs_bin_hdr = (struct bin_hdr *)(void *)hs_fw->data;
fw_hdr = (struct acr_fw_header *)(void *)(hs_fw->data +
hs_bin_hdr->header_offset);
@@ -215,54 +207,9 @@ int nvgpu_acr_self_hs_load_bootstrap(struct gk20a *g, struct nvgpu_falcon *flcn,
goto exit;
}
/* setup falcon apertures, boot-config */
err = nvgpu_falcon_setup_bootstrap_config(flcn);
err = nvgpu_falcon_hs_ucode_load_bootstrap(flcn, ucode, ucode_header);
if (err != 0) {
goto exit;
}
/* Copy Non Secure IMEM code */
err = nvgpu_falcon_copy_to_imem(flcn, 0U,
(u8 *)&ucode[ucode_header[OS_CODE_OFFSET] >> 2U],
ucode_header[OS_CODE_SIZE], 0U, false,
GET_IMEM_TAG(ucode_header[OS_CODE_OFFSET]));
if (err != 0) {
nvgpu_err(g, "HS ucode non-secure code to IMEM failed");
goto exit;
}
/* Put secure code after non-secure block */
sec_imem_dest = GET_NEXT_BLOCK(ucode_header[OS_CODE_SIZE]);
err = nvgpu_falcon_copy_to_imem(flcn, sec_imem_dest,
(u8 *)&ucode[ucode_header[APP_0_CODE_OFFSET] >> 2U],
ucode_header[APP_0_CODE_SIZE], 0U, true,
GET_IMEM_TAG(ucode_header[APP_0_CODE_OFFSET]));
if (err != 0) {
nvgpu_err(g, "HS ucode secure code to IMEM failed");
goto exit;
}
/* load DMEM: ensure that signatures are patched */
err = nvgpu_falcon_copy_to_dmem(flcn, 0U, (u8 *)&ucode[
ucode_header[OS_DATA_OFFSET] >> 2U],
ucode_header[OS_DATA_SIZE], 0U);
if (err != 0) {
nvgpu_err(g, "HS ucode data copy to DMEM failed");
goto exit;
}
/*
* Write non-zero value to mailbox register which is updated by
* HS bin to denote its return status.
*/
nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, 0xdeadbeefU);
/* set BOOTVEC to start of non-secure code */
err = nvgpu_falcon_bootstrap(flcn, 0U);
if (err != 0) {
nvgpu_err(g, "HS ucode bootstrap failed err-%d on falcon-%d", err,
nvgpu_falcon_get_id(flcn));
nvgpu_err(g, "HS ucode load & bootstrap failed");
goto exit;
}

75
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -390,6 +390,81 @@ exit:
return err;
}
int nvgpu_falcon_hs_ucode_load_bootstrap(struct nvgpu_falcon *flcn, u32 *ucode,
u32 *ucode_header)
{
struct gk20a *g;
u32 sec_imem_dest = 0U;
int err = 0;
if (!is_falcon_valid(flcn)) {
return -EINVAL;
}
g = flcn->g;
/* falcon reset */
err = nvgpu_falcon_reset(flcn);
if (err != 0) {
nvgpu_err(g, "nvgpu_falcon_reset() failed err=%d", err);
return err;
}
/* setup falcon apertures, boot-config */
err = nvgpu_falcon_setup_bootstrap_config(flcn);
if (err != 0) {
goto exit;
}
/* Copy Non Secure IMEM code */
err = nvgpu_falcon_copy_to_imem(flcn, 0U,
(u8 *)&ucode[ucode_header[OS_CODE_OFFSET] >> 2U],
ucode_header[OS_CODE_SIZE], 0U, false,
GET_IMEM_TAG(ucode_header[OS_CODE_OFFSET]));
if (err != 0) {
nvgpu_err(g, "HS ucode non-secure code to IMEM failed");
goto exit;
}
/* Put secure code after non-secure block */
sec_imem_dest = GET_NEXT_BLOCK(ucode_header[OS_CODE_SIZE]);
err = nvgpu_falcon_copy_to_imem(flcn, sec_imem_dest,
(u8 *)&ucode[ucode_header[APP_0_CODE_OFFSET] >> 2U],
ucode_header[APP_0_CODE_SIZE], 0U, true,
GET_IMEM_TAG(ucode_header[APP_0_CODE_OFFSET]));
if (err != 0) {
nvgpu_err(g, "HS ucode secure code to IMEM failed");
goto exit;
}
/* load DMEM: ensure that signatures are patched */
err = nvgpu_falcon_copy_to_dmem(flcn, 0U, (u8 *)&ucode[
ucode_header[OS_DATA_OFFSET] >> 2U],
ucode_header[OS_DATA_SIZE], 0U);
if (err != 0) {
nvgpu_err(g, "HS ucode data copy to DMEM failed");
goto exit;
}
/*
* Write non-zero value to mailbox register which is updated by
* HS bin to denote its return status.
*/
nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, 0xdeadbeefU);
/* set BOOTVEC to start of non-secure code */
err = nvgpu_falcon_bootstrap(flcn, 0U);
if (err != 0) {
nvgpu_err(g, "HS ucode bootstrap failed err-%d on falcon-%d", err,
nvgpu_falcon_get_id(flcn));
goto exit;
}
exit:
return err;
}
int nvgpu_falcon_get_mem_size(struct nvgpu_falcon *flcn,
enum falcon_mem_type type, u32 *size)
{

15
drivers/gpu/nvgpu/include/nvgpu/falcon.h
View File

@@ -409,6 +409,21 @@ void nvgpu_falcon_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index,
int nvgpu_falcon_bl_bootstrap(struct nvgpu_falcon *flcn,
struct nvgpu_falcon_bl_info *bl_info);
/**
* @brief Bootstrap the falcon with HS ucode.
*
* @param flcn [in] The falcon
* @param ucode [in] ucode to be copied
* @param ucode_header [in] ucode header
*
* Copies HS ucode source and descriptor to IMEM and DMEM and then
* bootstraps the falcon.
*
* @return 0 in case of success, < 0 in case of failure.
*/
int nvgpu_falcon_hs_ucode_load_bootstrap(struct nvgpu_falcon *flcn, u32 *ucode,
u32 *ucode_header);
/**
* @brief Get the size of falcon's memory.
*