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gpu: nvgpu: Reorg mc HAL initialization

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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the mc
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I26d74c14661a193af7e8d90dd672b73010e5f841
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509601
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Sunny He
2017-06-27 13:42:33 -07:00
committed by mobile promotions
parent ecf67ebbf6
commit e78153ea1b
8 changed files with 66 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/Makefile.nvgpu
View File

@@ -110,7 +110,6 @@ nvgpu-y := \
gm20b/pmu_gm20b.o \
gm20b/mm_gm20b.o \
gm20b/regops_gm20b.o \
gm20b/mc_gm20b.o \
gm20b/cde_gm20b.o \
gm20b/therm_gm20b.o \
gm206/bios_gm206.o \

20
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -16,6 +16,7 @@
#include "gk20a/gk20a.h"
#include "gk20a/dbg_gpu_gk20a.h"
#include "gk20a/css_gr_gk20a.h"
#include "gk20a/mc_gk20a.h"
#include "gk20a/bus_gk20a.h"
#include "gk20a/flcn_gk20a.h"
#include "gk20a/priv_ring_gk20a.h"
@@ -31,7 +32,6 @@
#include "mm_gm20b.h"
#include "pmu_gm20b.h"
#include "clk_gm20b.h"
#include "mc_gm20b.h"
#include "regops_gm20b.h"
#include "cde_gm20b.h"
#include "therm_gm20b.h"
@@ -199,6 +199,22 @@ static const struct gpu_ops gm20b_ops = {
.pg_gr_load_gating_prod =
gr_gm20b_pg_gr_load_gating_prod,
},
.mc = {
.intr_enable = mc_gk20a_intr_enable,
.intr_unit_config = mc_gk20a_intr_unit_config,
.isr_stall = mc_gk20a_isr_stall,
.intr_stall = mc_gk20a_intr_stall,
.intr_stall_pause = mc_gk20a_intr_stall_pause,
.intr_stall_resume = mc_gk20a_intr_stall_resume,
.intr_nonstall = mc_gk20a_intr_nonstall,
.intr_nonstall_pause = mc_gk20a_intr_nonstall_pause,
.intr_nonstall_resume = mc_gk20a_intr_nonstall_resume,
.enable = gk20a_mc_enable,
.disable = gk20a_mc_disable,
.reset = gk20a_mc_reset,
.boot_0 = gk20a_mc_boot_0,
.is_intr1_pending = mc_gk20a_is_intr1_pending,
},
.cde = {
.get_program_numbers = gm20b_cde_get_program_numbers,
},
@@ -217,6 +233,7 @@ int gm20b_init_hal(struct gk20a *g)
gops->ltc = gm20b_ops.ltc;
gops->clock_gating = gm20b_ops.clock_gating;
gops->mc = gm20b_ops.mc;
gops->cde = gm20b_ops.cde;
gops->falcon = gm20b_ops.falcon;
@@ -255,7 +272,6 @@ int gm20b_init_hal(struct gk20a *g)
}
#endif
gk20a_init_bus(gops);
gm20b_init_mc(gops);
gk20a_init_priv_ring(gops);
gm20b_init_gr(gops);
gm20b_init_fb(gops);

36
drivers/gpu/nvgpu/gm20b/mc_gm20b.c
View File

@@ -1,36 +0,0 @@
/*
* GK20A memory interface
*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "gk20a/gk20a.h"
#include "gk20a/mc_gk20a.h"
#include "mc_gm20b.h"
void gm20b_init_mc(struct gpu_ops *gops)
{
gops->mc.intr_enable = mc_gk20a_intr_enable;
gops->mc.intr_unit_config = mc_gk20a_intr_unit_config;
gops->mc.isr_stall = mc_gk20a_isr_stall;
gops->mc.intr_stall = mc_gk20a_intr_stall;
gops->mc.intr_stall_pause = mc_gk20a_intr_stall_pause;
gops->mc.intr_stall_resume = mc_gk20a_intr_stall_resume;
gops->mc.intr_nonstall = mc_gk20a_intr_nonstall;
gops->mc.intr_nonstall_pause = mc_gk20a_intr_nonstall_pause;
gops->mc.intr_nonstall_resume = mc_gk20a_intr_nonstall_resume;
gops->mc.enable = gk20a_mc_enable;
gops->mc.disable = gk20a_mc_disable;
gops->mc.reset = gk20a_mc_reset;
gops->mc.boot_0 = gk20a_mc_boot_0;
gops->mc.is_intr1_pending = mc_gk20a_is_intr1_pending;
}

18
drivers/gpu/nvgpu/gm20b/mc_gm20b.h
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef MC_GM20B_H
#define MC_GM20B_H
void gm20b_init_mc(struct gpu_ops *gops);
#endif

20
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -18,6 +18,8 @@
#include "gk20a/css_gr_gk20a.h"
#include "gk20a/bus_gk20a.h"
#include "gk20a/pramin_gk20a.h"
#include "gk20a/flcn_gk20a.h"
#include "gk20a/mc_gk20a.h"
#include "gp10b/ltc_gp10b.h"
#include "gp10b/gr_gp10b.h"
@@ -239,6 +241,22 @@ static const struct gpu_ops gp106_ops = {
.pg_gr_load_gating_prod =
gr_gp106_pg_gr_load_gating_prod,
},
.mc = {
.intr_enable = mc_gp10b_intr_enable,
.intr_unit_config = mc_gp10b_intr_unit_config,
.isr_stall = mc_gp10b_isr_stall,
.intr_stall = mc_gp10b_intr_stall,
.intr_stall_pause = mc_gp10b_intr_stall_pause,
.intr_stall_resume = mc_gp10b_intr_stall_resume,
.intr_nonstall = mc_gp10b_intr_nonstall,
.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
.enable = gk20a_mc_enable,
.disable = gk20a_mc_disable,
.reset = gk20a_mc_reset,
.boot_0 = gk20a_mc_boot_0,
.is_intr1_pending = mc_gp10b_is_intr1_pending,
},
.cde = {
.get_program_numbers = gp10b_cde_get_program_numbers,
.need_scatter_buffer = gp10b_need_scatter_buffer,
@@ -276,6 +294,7 @@ int gp106_init_hal(struct gk20a *g)
gops->ltc = gp106_ops.ltc;
gops->clock_gating = gp106_ops.clock_gating;
gops->mc = gp106_ops.mc;
gops->cde = gp106_ops.cde;
gops->xve = gp106_ops.xve;
gops->falcon = gp106_ops.falcon;
@@ -290,7 +309,6 @@ int gp106_init_hal(struct gk20a *g)
gops->securegpccs = 1;
gops->pmupstate = true;
gk20a_init_bus(gops);
gp10b_init_mc(gops);
gp10b_init_priv_ring(gops);
gp106_init_gr(gops);
gp10b_init_fecs_trace_ops(gops);

19
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -19,6 +19,7 @@
#include "gk20a/bus_gk20a.h"
#include "gk20a/pramin_gk20a.h"
#include "gk20a/flcn_gk20a.h"
#include "gk20a/mc_gk20a.h"
#include "gp10b/gr_gp10b.h"
#include "gp10b/fecs_trace_gp10b.h"
@@ -207,6 +208,22 @@ static const struct gpu_ops gp10b_ops = {
.pg_gr_load_gating_prod =
gr_gp10b_pg_gr_load_gating_prod,
},
.mc = {
.intr_enable = mc_gp10b_intr_enable,
.intr_unit_config = mc_gp10b_intr_unit_config,
.isr_stall = mc_gp10b_isr_stall,
.intr_stall = mc_gp10b_intr_stall,
.intr_stall_pause = mc_gp10b_intr_stall_pause,
.intr_stall_resume = mc_gp10b_intr_stall_resume,
.intr_nonstall = mc_gp10b_intr_nonstall,
.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
.enable = gk20a_mc_enable,
.disable = gk20a_mc_disable,
.reset = gk20a_mc_reset,
.boot_0 = gk20a_mc_boot_0,
.is_intr1_pending = mc_gp10b_is_intr1_pending,
},
.cde = {
.get_program_numbers = gp10b_cde_get_program_numbers,
.need_scatter_buffer = gp10b_need_scatter_buffer,
@@ -227,6 +244,7 @@ int gp10b_init_hal(struct gk20a *g)
gops->ltc = gp10b_ops.ltc;
gops->clock_gating = gp10b_ops.clock_gating;
gops->mc = gp10b_ops.mc;
gops->cde = gp10b_ops.cde;
gops->falcon = gp10b_ops.falcon;
@@ -274,7 +292,6 @@ int gp10b_init_hal(struct gk20a *g)
#endif
gk20a_init_bus(gops);
gp10b_init_mc(gops);
gp10b_init_priv_ring(gops);
gp10b_init_gr(gops);
gp10b_init_fecs_trace_ops(gops);

20
drivers/gpu/nvgpu/gp10b/mc_gp10b.c
View File

@@ -156,7 +156,7 @@ void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
static bool mc_gp10b_is_intr1_pending(struct gk20a *g,
bool mc_gp10b_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1)
{
u32 mask = 0;
@@ -179,21 +179,3 @@ static bool mc_gp10b_is_intr1_pending(struct gk20a *g,
return is_pending;
}
void gp10b_init_mc(struct gpu_ops *gops)
{
gops->mc.intr_enable = mc_gp10b_intr_enable;
gops->mc.intr_unit_config = mc_gp10b_intr_unit_config;
gops->mc.isr_stall = mc_gp10b_isr_stall;
gops->mc.intr_stall = mc_gp10b_intr_stall;
gops->mc.intr_stall_pause = mc_gp10b_intr_stall_pause;
gops->mc.intr_stall_resume = mc_gp10b_intr_stall_resume;
gops->mc.intr_nonstall = mc_gp10b_intr_nonstall;
gops->mc.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause;
gops->mc.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume;
gops->mc.enable = gk20a_mc_enable;
gops->mc.disable = gk20a_mc_disable;
gops->mc.reset = gk20a_mc_reset;
gops->mc.boot_0 = gk20a_mc_boot_0;
gops->mc.is_intr1_pending = mc_gp10b_is_intr1_pending;
}

11
drivers/gpu/nvgpu/gp10b/mc_gp10b.h
View File

@@ -20,9 +20,18 @@ enum MC_INTERRUPT_REGLIST {
NVGPU_MC_INTR_NONSTALLING,
};
void gp10b_init_mc(struct gpu_ops *gops);
void mc_gp10b_intr_enable(struct gk20a *g);
void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask);
void mc_gp10b_isr_stall(struct gk20a *g);
bool mc_gp10b_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1);
u32 mc_gp10b_intr_stall(struct gk20a *g);
void mc_gp10b_intr_stall_pause(struct gk20a *g);
void mc_gp10b_intr_stall_resume(struct gk20a *g);
u32 mc_gp10b_intr_nonstall(struct gk20a *g);
void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
#endif