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gpu: nvgpu: Read current_volt from vol_rail_get_status
-Latest ucode doesn't support get_voltage RPC, the data can be extracted from data obtained by volt_rail_get_status board_obj cmd. Updating the debugfs node to read the data from volt_rail_get_status. JIRA NVGPU-3815 Change-Id: I85f84a757425411725773802c20f05063b222afc Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2153387 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -329,6 +329,8 @@ static int volt_rail_obj_update(struct gk20a *g,
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/* Updating only vmin as per requirement, later other fields can be added */
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volt_rail_obj->vmin_limitu_v = pstatus->vmin_limitu_v;
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volt_rail_obj->max_limitu_v = pstatus->max_limitu_v;
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volt_rail_obj->current_volt_uv = pstatus->curr_volt_defaultu_v;
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return 0;
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}
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@@ -585,6 +587,32 @@ int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv)
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return status;
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}
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int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv)
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{
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struct boardobjgrp *pboardobjgrp;
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struct boardobj *pboardobj = NULL;
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struct voltage_rail *volt_rail = NULL;
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int status;
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u8 index;
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status = nvgpu_volt_rail_boardobj_grp_get_status(g);
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if (status != 0) {
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nvgpu_err(g, "volt rail get status failed");
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return status;
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}
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pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
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BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
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volt_rail = (struct voltage_rail *)(void *)pboardobj;
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if (volt_rail->current_volt_uv != 0U) {
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*vcurr_uv = volt_rail->current_volt_uv;
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return status;
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}
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}
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return status;
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}
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u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g)
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{
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struct boardobjgrp *pboardobjgrp;
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@@ -87,6 +87,7 @@ struct voltage_rail {
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s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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u32 vmin_limitu_v;
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u32 max_limitu_v;
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u32 current_volt_uv;
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};
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int nvgpu_volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
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@@ -110,5 +111,6 @@ int nvgpu_volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
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u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal
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(struct gk20a *g, u8 vbios_volt_domain);
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void nvgpu_pmu_volt_rpc_handler(struct gk20a *g, struct nv_pmu_rpc_header *rpc);
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int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv);
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#endif /* NVGPU_PMU_VOLT_H */
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@@ -25,7 +25,7 @@ static int get_curr_voltage(void *data, u64 *val)
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u32 readval;
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int err;
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err = nvgpu_volt_get_voltage(g, CTRL_VOLT_DOMAIN_LOGIC, &readval);
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err = nvgpu_volt_get_curr_volt_ps35(g, &readval);
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if (!err)
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*val = readval;
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