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gpu: nvgpu: ACR load split feature support

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-Added method nvgpu_tu104_acr_ahesasc_sw_init()
 to set ACR-AHESASC properties.
-Added method nvgpu_tu104_acr_asb_sw_init() to
 set ACR-ASB properties.
-Modified method nvgpu_tu104_acr_sw_init() to
 call ACR AHESASC/ASB init & set bootstrap_owner
 to LSF_FALCON_ID_GSPLITE by removing older support
 of default ACR executing on SEC2.
-Added method tu104_bootstrap_hs_acr to execute
 ACR AHESASC & ASB ucode.
-Execute ACR-AHESASC(ACR hub encryption setter and
 signature checker) on SEC2 falcon to copy ucode
 blob from non-wpr to wpr & lockdown wpr then
 perform signature verification of LS falcon ucode
 whitout doing any LS flacon bootstrap.
-Once first stage of ACR is successful then execute
 ACR-ASB(ACR SEC2 booter) on GSP falcon to bootstrap
 SEC2-RTOS on sec2 falcon to perform PMU & GR
 falcons bootstrap.
-Enable SEC2 RTOS support by setting
 NVGPU_SUPPORT_SEC2_RTOS to true
-Added tu104 ACR remove support to clear
 allocated space

JIRA NVGPUT-134

Change-Id: I2d1777af83feda5e8f6845876177cce062c43ace
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918937
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2018-10-04 10:46:29 +05:30
committed by mobile promotions
parent ec2b3a748f
commit e7d706ccaf
2 changed files with 113 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

117
drivers/gpu/nvgpu/tu104/acr_tu104.c
View File

@@ -21,6 +21,7 @@
*/
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/firmware.h>
#include <nvgpu/enabled.h>
#include <nvgpu/utils.h>
#include <nvgpu/debug.h>
@@ -28,19 +29,125 @@
#include <nvgpu/pmu.h>
#include <nvgpu/dma.h>
#include "tu104/acr_tu104.h"
#include "gk20a/gk20a.h"
#include "gm20b/acr_gm20b.h"
#include "gp106/acr_gp106.h"
#include "gv100/gsp_gv100.h"
#include "tu104/acr_tu104.h"
#include "tu104/sec2_tu104.h"
static int tu104_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_type)
{
int err = 0;
nvgpu_log_fn(g, " ");
err = gm20b_bootstrap_hs_acr(g, &g->acr, &g->acr.acr_ahesasc);
if (err != 0) {
nvgpu_err(g, "ACR AHESASC bootstrap failed");
goto exit;
}
err = gm20b_bootstrap_hs_acr(g, &g->acr, &g->acr.acr_asb);
if (err != 0) {
nvgpu_err(g, "ACR ASB bootstrap failed");
goto exit;
}
exit:
return err;
}
/* ACR-AHESASC(ACR hub encryption setter and signature checker) init*/
static void nvgpu_tu104_acr_ahesasc_sw_init(struct gk20a *g,
struct hs_acr *acr_ahesasc)
{
struct hs_flcn_bl *hs_bl = &acr_ahesasc->acr_hs_bl;
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
acr_ahesasc->acr_type = ACR_AHESASC;
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_PROD_UCODE;
} else {
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_DBG_UCODE;
}
acr_ahesasc->ptr_bl_dmem_desc = &acr_ahesasc->bl_dmem_desc_v1;
acr_ahesasc->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
acr_ahesasc->acr_flcn = &g->sec2_flcn;
acr_ahesasc->acr_flcn_setup_hw_and_bl_bootstrap =
tu104_sec2_setup_hw_and_bl_bootstrap;
}
/* ACR-ASB(ACR SEC2 booter) init*/
static void nvgpu_tu104_acr_asb_sw_init(struct gk20a *g,
struct hs_acr *acr_asb)
{
struct hs_flcn_bl *hs_bl = &acr_asb->acr_hs_bl;
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
acr_asb->acr_type = ACR_ASB;
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_asb->acr_fw_name = HSBIN_ACR_ASB_PROD_UCODE;
} else {
acr_asb->acr_fw_name = HSBIN_ACR_ASB_DBG_UCODE;
}
acr_asb->ptr_bl_dmem_desc = &acr_asb->bl_dmem_desc_v1;
acr_asb->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
acr_asb->acr_flcn = &g->gsp_flcn;
acr_asb->acr_flcn_setup_hw_and_bl_bootstrap =
gv100_gsp_setup_hw_and_bl_bootstrap;
}
static void tu104_free_hs_acr(struct gk20a *g,
struct hs_acr *acr_type)
{
struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = mm->pmu.vm;
if (acr_type->acr_fw != NULL) {
nvgpu_release_firmware(g, acr_type->acr_fw);
}
if (acr_type->acr_hs_bl.hs_bl_fw != NULL) {
nvgpu_release_firmware(g, acr_type->acr_hs_bl.hs_bl_fw);
}
nvgpu_dma_unmap_free(vm, &acr_type->acr_ucode);
nvgpu_dma_unmap_free(vm, &acr_type->acr_hs_bl.hs_bl_ucode);
}
static void tu104_remove_acr_support(struct nvgpu_acr *acr)
{
struct gk20a *g = acr->g;
tu104_free_hs_acr(g, &acr->acr_ahesasc);
tu104_free_hs_acr(g, &acr->acr_asb);
}
void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_log_fn(g, " ");
/* Inherit settings from older chip */
nvgpu_gp106_acr_sw_init(g, acr);
acr->bootstrap_owner = LSF_FALCON_ID_SEC2;
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
acr->bootstrap_owner = LSF_FALCON_ID_GSPLITE;
acr->max_supported_lsfm = TU104_MAX_SUPPORTED_LSFM;
acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr;
acr->remove_support = tu104_remove_acr_support;
acr->acr.acr_flcn_setup_hw_and_bl_bootstrap =
tu104_sec2_setup_hw_and_bl_bootstrap;
/* Init ACR-AHESASC */
nvgpu_tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc);
/* Init ACR-ASB*/
nvgpu_tu104_acr_asb_sw_init(g, &acr->acr_asb);
}

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -1012,8 +1012,8 @@ int tu104_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
__nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, true);
__nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, false);
__nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
__nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, true);
/* for now */
__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);