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gpu: nvgpu: rename gk20a_pmu_cmd_post()

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- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post()
- replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post()
  wherever called.

JIRA NVGPU-93

Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2017-07-04 11:25:00 +05:30
committed by mobile promotions
parent 2cf964d175
commit e808d345f1
17 changed files with 35 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/boardobj/boardobjgrp.c
View File

@@ -744,7 +744,7 @@ static u32 boardobjgrp_pmucmdsend(struct gk20a *g,
handlerparams.pcmd = pcmd;
handlerparams.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
boardobjgrp_pmucmdhandler,
(void *)&handlerparams,

6
drivers/gpu/nvgpu/clk/clk.c
View File

@@ -97,7 +97,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
handler.prpccall = &rpccall;
handler.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
clkrpc_pmucmdhandler, (void *)&handler,
&seqdesc, ~0);
@@ -160,7 +160,7 @@ u32 clk_pmu_vin_load(struct gk20a *g)
handler.prpccall = &rpccall;
handler.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
clkrpc_pmucmdhandler, (void *)&handler,
&seqdesc, ~0);
@@ -262,7 +262,7 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
handler.prpccall = &rpccall;
handler.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
clkrpc_pmucmdhandler, (void *)&handler,
&seqdesc, ~0);

2
drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
View File

@@ -478,7 +478,7 @@ clean_up:
return err;
}
int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
struct pmu_msg *msg, struct pmu_payload *payload,
u32 queue_id, pmu_callback callback, void *cb_param,
u32 *seq_desc, unsigned long timeout)

6
drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
View File

@@ -112,7 +112,7 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu)
payload.in.offset = pv->get_perfmon_cmd_init_offsetofvar(COUNTER_ALLOC);
nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT");
gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ,
NULL, NULL, &seq, ~0);
return 0;
@@ -160,7 +160,7 @@ int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu)
pv->get_perfmon_cmd_start_offsetofvar(COUNTER_ALLOC);
nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START");
gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ,
NULL, NULL, &seq, ~0);
return 0;
@@ -183,7 +183,7 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu)
cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP;
nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
NULL, NULL, &seq, ~0);
return 0;
}

16
drivers/gpu/nvgpu/common/pmu/pmu_pg.c
View File

@@ -151,7 +151,7 @@ static int pmu_enable_elpg_locked(struct gk20a *g, u32 pg_engine_id)
pmu->mscg_transition_state = PMU_ELPG_STAT_ON_PENDING;
nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_ALLOW");
status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg,
pmu, &seq, ~0);
WARN_ON(status != 0);
@@ -305,7 +305,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g)
ptr = &pmu->mscg_transition_state;
nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_DISALLOW");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg,
pmu, &seq, ~0);
@@ -376,7 +376,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id)
cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_INIT;
nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_INIT");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_pg_elpg_msg, pmu, &seq, ~0);
/* alloc dmem for powergating state log */
@@ -390,7 +390,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id)
cmd.cmd.pg.stat.data = 0;
nvgpu_pmu_dbg(g, "cmd post PMU_PG_STAT_CMD_ALLOC_DMEM");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
pmu_handle_pg_stat_msg, pmu, &seq, ~0);
/* disallow ELPG initially
@@ -409,7 +409,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id)
cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_DISALLOW;
nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_DISALLOW");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_pg_elpg_msg, pmu, &seq, ~0);
if (g->ops.pmu.pmu_pg_set_sub_feature_mask)
@@ -508,7 +508,7 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g)
pmu->buf_loaded = false;
nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_FECS");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
pmu_handle_pg_buf_config_msg, pmu, &desc, ~0);
nvgpu_pmu_state_change(g, PMU_STATE_LOADING_PG_BUF, false);
return err;
@@ -544,7 +544,7 @@ void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g)
pmu->buf_loaded = false;
nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_ZBC");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
pmu_handle_pg_buf_config_msg, pmu, &desc, ~0);
nvgpu_pmu_state_change(g, PMU_STATE_LOADING_ZBC, false);
}
@@ -662,7 +662,7 @@ int nvgpu_pmu_ap_send_command(struct gk20a *g,
return 0x2f;
}
status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
p_callback, pmu, &seq, ~0);
if (status) {

2
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
View File

@@ -607,7 +607,7 @@ void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
pmu->zbc_save_done = 0;
gk20a_dbg_pmu("cmd post ZBC_TABLE_UPDATE");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_zbc_msg, pmu, &seq, ~0);
pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g),
&pmu->zbc_save_done, 1);

4
drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
View File

@@ -153,7 +153,7 @@ int gm20b_pmu_init_acr(struct gk20a *g)
cmd.cmd.acr.init_wpr.regionid = 0x01;
cmd.cmd.acr.init_wpr.wproffset = 0x00;
gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0);
gk20a_dbg_fn("done");
@@ -217,7 +217,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags)
cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id;
gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n",
falcon_id);
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
}

2
drivers/gpu/nvgpu/gp106/mclk_gp106.c
View File

@@ -3371,7 +3371,7 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
reg_alloc);
/* Send command to PMU to execute sequencer script */
status = gk20a_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
mclk_seq_pmucmdhandler,
&seq_completion_status, &seqdesc, ~0);

6
drivers/gpu/nvgpu/gp106/pmu_gp106.c
View File

@@ -126,7 +126,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
PMU_PG_FEATURE_GR_RPPG_ENABLED;
gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_param_msg, pmu, &seq, ~0);
} else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) {
cmd.hdr.unit_id = PMU_UNIT_PG;
@@ -143,7 +143,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING;
gp106_dbg_pmu("cmd post MS PMU_PG_CMD_ID_PG_PARAM");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_param_msg, pmu, &seq, ~0);
}
@@ -250,7 +250,7 @@ static void gp106_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
gp106_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
falconidmask);
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
}

4
drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
View File

@@ -166,7 +166,7 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
u64_hi32(g->pmu.wpr_buf.gpu_va);
gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
falconidmask);
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
}
@@ -242,7 +242,7 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM ");
gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_gr_param_msg, pmu, &seq, ~0);
} else

2
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -383,7 +383,7 @@ int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id,
bool nvgpu_pmu_queue_is_empty(struct nvgpu_pmu *pmu, struct pmu_queue *queue);
/* send a cmd to pmu */
int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
struct pmu_msg *msg, struct pmu_payload *payload,
u32 queue_id, pmu_callback callback, void *cb_param,
u32 *seq_desc, unsigned long timeout);

4
drivers/gpu/nvgpu/lpwr/lpwr.c
View File

@@ -243,7 +243,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
cmd.cmd.pg.mclk_change.data = payload;
nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE");
status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
@@ -276,7 +276,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g)
PMU_PG_PARAM_CMD_POST_INIT;
nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT");
status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
PMU_COMMAND_QUEUE_LPQ,
nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);

2
drivers/gpu/nvgpu/lpwr/rppg.c
View File

@@ -73,7 +73,7 @@ static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
return -1;
}
status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
pmu_handle_rppg_init_msg, &success, &seq, ~0);
if (status) {
nvgpu_err(g, "Unable to submit parameter command %d",

2
drivers/gpu/nvgpu/perf/perf.c
View File

@@ -96,7 +96,7 @@ u32 perf_pmu_vfe_load(struct gk20a *g)
handler.prpccall = &rpccall;
handler.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
perfrpc_pmucmdhandler, (void *)&handler,
&seqdesc, ~0);

6
drivers/gpu/nvgpu/pmgr/pmgrpmu.c
View File

@@ -109,7 +109,7 @@ static u32 pmgr_pmu_set_object(struct gk20a *g,
/* Setup the handler params to communicate back results.*/
handlerparams.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
pmgr_pmucmdhandler,
(void *)&handlerparams,
@@ -392,7 +392,7 @@ u32 pmgr_pmu_pwr_devices_query_blocking(
/* Setup the handler params to communicate back results.*/
handlerparams.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
pmgr_pmucmdhandler,
(void *)&handlerparams,
@@ -436,7 +436,7 @@ static u32 pmgr_pmu_load_blocking(struct gk20a *g)
/* Setup the handler params to communicate back results.*/
handlerparams.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
PMU_COMMAND_QUEUE_LPQ,
pmgr_pmucmdhandler,
(void *)&handlerparams,

2
drivers/gpu/nvgpu/therm/thrmpmu.c
View File

@@ -81,7 +81,7 @@ static u32 therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
u32 status;
struct therm_pmucmdhandler_params *handlerparams = NULL;
status = gk20a_pmu_cmd_post(g, cmd, msg, payload,
status = nvgpu_pmu_cmd_post(g, cmd, msg, payload,
queue_id,
callback,
cb_param,

2
drivers/gpu/nvgpu/volt/volt_pmu.c
View File

@@ -83,7 +83,7 @@ static u32 volt_pmu_rpc_execute(struct gk20a *g,
handler.prpc_call = prpc_call;
handler.success = 0;
status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
volt_rpc_pmucmdhandler, (void *)&handler,
&seqdesc, ~0);