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gpu: nvgpu: NVGPU ACR interface doxygen update
-Adding detailed description for NVGPU-ACR interfaces required for doxygen JIRA NVGPU-4152 Change-Id: I2c0b5d173f04bf6ea995995ee9dfa0652e424db4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2219874 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
committed by
Alex Waterman
Alex Waterman
parent
c238dd8c55
commit
e83278f4e4
@@ -23,9 +23,28 @@
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#ifndef NVGPU_ACR_INTERFACE_H
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#define NVGPU_ACR_INTERFACE_H
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/* BLOB construct interface */
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/**
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* Blob construct interfaces:
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* NVGPU creates LS ucode blob in system/FB's non-WPR memory. LS ucodes
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* will be read from filesystem and added to blob for the detected chip.
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* Below are the structs needs to be filled by NvGPU for each LS Falcon
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* ucode supported for the detected chip. Upon successful filling structs,
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* NvGPU should copy below structs along with ucode to the non-WPR blob
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* in below mentioned pattern. LS ucodes blob is required by the ACR HS
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* ucode to authenticate & load LS ucode on to respective engine's LS Falcon.
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*
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* + WPR header struct #lsf_wpr_header.
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* + LSB header struct #lsf_lsb_header.
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* + Boot loader struct #flcn_bl_dmem_desc.
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* + ucode image.
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*
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* + BLOB Pattern:
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* ---------------------------------------------
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* | LSF WPR HDR | LSF LSB HDR | BL desc | ucode |
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* ---------------------------------------------
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*/
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/*
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/**
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* Light Secure WPR Content Alignments
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*/
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#define LSF_WPR_HEADER_ALIGNMENT (256U)
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@@ -37,9 +56,10 @@
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#define LSF_DATA_SIZE_ALIGNMENT (256U)
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#define LSF_CODE_SIZE_ALIGNMENT (256U)
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/** UCODE surface should be aligned to 4k PAGE_SIZE */
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#define LSF_UCODE_DATA_ALIGNMENT 4096U
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/*
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/**
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* Maximum WPR Header size
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*/
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#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \
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@@ -83,143 +103,341 @@ enum {
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#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1U)
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#endif
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/*Light Secure Bootstrap header related defines*/
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0U
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE BIT32(0)
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2)
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#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3)
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#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U
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/*
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* Image Status Defines
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/**
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* Image status updated by ACR HS ucode to know the LS
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* Falcon ucode status.
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*/
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#define LSF_IMAGE_STATUS_NONE (0U)
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/** IMAGE copied from NON-WPR to WPR BLOB*/
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#define LSF_IMAGE_STATUS_COPY (1U)
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/** LS Falcon ucode verification failed*/
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#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U)
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/** LS Falcon data verification failed*/
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#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U)
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/** Both ucode and data validation passed */
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#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U)
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/**
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* LS Falcons such as FECS and GPCCS does not have signatures for binaries in
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* debug environment(fmodel).
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*/
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#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U)
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/** LS Falcon validation passed & ready for bootstrap */
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#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U)
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/**
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* Light Secure WPR Header
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* Defines state allowing Light Secure Falcon bootstrapping.
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*/
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struct lsf_wpr_header {
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/** LS falcon ID */
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u32 falcon_id;
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/**
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* LS Falcon LSB header offset from non-WPR base, below equation used
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* to get LSB header offset for each managed LS falcon.
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* Offset = Non-WPR base + #LSF_LSB_HEADER_ALIGNMENT +
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* ((#LSF_UCODE_DATA_ALIGNMENT + #LSF_BL_DATA_ALIGNMENT) *
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* LS Falcon index)
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*
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*/
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u32 lsb_offset;
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/**
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* LS Falcon bootstrap owner, which performs bootstrapping of
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* supported LS Falcon from ACR HS ucode. Below are the bootstrapping
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* supporting Falcon owners.
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* + Falcon #FALCON_ID_PMU
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* + Falcon #FALCON_ID_GSPLITE
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*
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* On GV11B, bootstrap_owner set to #FALCON_ID_PMU as ACR HS ucode
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* runs on PMU Engine Falcon.
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*
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*/
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u32 bootstrap_owner;
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/**
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* Skip bootstrapping by ACR HS ucode,
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* 1 - skip LS Falcon bootstrapping by ACR HS ucode
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* 0 - LS Falcon bootstrapping is done by ACR HS ucode.
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*/
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u32 lazy_bootstrap;
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/** LS ucode bin version*/
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u32 bin_version;
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/**
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* Bootstrapping status updated by ACR HS ucode to know the LS
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* Falcon ucode status.
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*/
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u32 status;
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};
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/**
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* Code/data signature details of LS falcon
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*/
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struct lsf_ucode_desc {
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/** ucode's production signature */
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u8 prd_keys[2][16];
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/** ucode's debug signature */
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u8 dbg_keys[2][16];
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/**
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* production signature present status,
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* 1 - production signature present
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* 0 - production signature not present
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*/
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u32 b_prd_present;
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/**
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* debug signature present
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* 1 - debug signature present
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* 0 - debug signature not present
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*/
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u32 b_dbg_present;
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/** LS Falcon ID */
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u32 falcon_id;
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/**
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* include version in signature calculation if supported
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* 1 - supported
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* 0 - not supported
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*/
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u32 bsupports_versioning;
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/** version to include it in signature calculation if supported */
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u32 version;
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/** valid dependency map data to consider from dep_map array member */
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u32 dep_map_count;
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/**
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* packed dependency map used to compute the DM hashes on the code and
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* data.
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*/
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u8 dep_map[FALCON_ID_END * 2 * 4];
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/** Message used to derive key */
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u8 kdf[16];
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};
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/**
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* Light Secure Bootstrap Header
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* Defines state allowing Light Secure Falcon bootstrapping.
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*/
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/** Load BL at 0th IMEM offset */
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0U
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE BIT32(0)
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/** This falcon requires a ctx before issuing DMAs. */
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2)
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/** Use priv loading method instead of bootloader/DMAs */
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#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3)
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#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U
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struct lsf_lsb_header {
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/** Code/data signature details of each LS falcon */
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struct lsf_ucode_desc signature;
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/**
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* Offset from non-WPR base where UCODE is located,
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* Offset = Non-WPR base + #LSF_LSB_HEADER_ALIGNMENT +
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* #LSF_UCODE_DATA_ALIGNMENT + ( #LSF_BL_DATA_ALIGNMENT *
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* LS Falcon index)
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*/
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u32 ucode_off;
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/**
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* Size of ucode, ucode will be copied to LS Falcon IMEM of this
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* size. Copy is done by ACR HS ucode upon signature verification
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* pass on ucode.
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*/
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u32 ucode_size;
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/**
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* Size of ucode data, ucode will be copied to LS Falcon DMEM of this
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* size. Copy is done by ACR HS ucode upon signature verification
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* pass on ucode data.
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*/
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u32 data_size;
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/** Size of bootloader that needs to be loaded by bootstrap owner */
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u32 bl_code_size;
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/** BL starting virtual address. Need for tagging */
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u32 bl_imem_off;
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/**
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* Offset from non-WPR base holding the BL data
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* Offset = (Non-WPR base + #LSF_LSB_HEADER_ALIGNMENT +
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* #LSF_UCODE_DATA_ALIGNMENT + #LSF_BL_DATA_ALIGNMENT) *
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* #LS Falcon index
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*/
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u32 bl_data_off;
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/**
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* Size of BL data, BL data will be copied to LS Falcon DMEM of
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* bl data size
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*/
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u32 bl_data_size;
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/**
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* Offset from non-WPR base address where UCODE Application code is
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* located.
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*/
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u32 app_code_off;
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/** Size of UCODE Application code */
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u32 app_code_size;
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/**
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* Offset from non-WPR base address where UCODE Application data
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* is located
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*/
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u32 app_data_off;
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/** Size of UCODE Application data */
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u32 app_data_size;
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/**
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* NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0 - Load BL at 0th IMEM offset
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* NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX - This falcon requires a ctx
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* before issuing DMAs.
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* NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD - Use priv loading method
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* instead of bootloader/DMAs
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*/
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u32 flags;
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};
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/**
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* Structure used by the boot-loader to load the rest of the LS Falcon code.
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*
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* This has to be filled by the GPU driver and copied into WPR region offset
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* holding the BL data.
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*/
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struct flcn_bl_dmem_desc {
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u32 reserved[4]; /*Should be the first element..*/
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u32 signature[4]; /*Should be the first element..*/
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u32 ctx_dma;
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/** Should be always first element */
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u32 reserved[4];
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/**
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* Signature should follow reserved 16B signature for secure code.
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* 0s if no secure code
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*/
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u32 signature[4];
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/**
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* Type of memory-aperture DMA index used by the bootloader
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* while loading code/data.
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*/
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u32 ctx_dma;
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/** 256B aligned physical sysmem/FB address where code is located. */
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struct falc_u64 code_dma_base;
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 sec_code_off;
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u32 sec_code_size;
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u32 code_entry_point;
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/**
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* Offset from code_dma_base where the nonSecure code is located.
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* The offset must be multiple of 256 to help performance.
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*/
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u32 non_sec_code_off;
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/** The size of the non-secure code part. */
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u32 non_sec_code_size;
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/**
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* Offset from code_dma_base where the secure code is located.
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* The offset must be multiple of 256 to help performance.
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*/
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u32 sec_code_off;
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/** The size of the secure code part. */
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u32 sec_code_size;
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/**
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* Code entry point which will be invoked by BL after code is
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* loaded.
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*/
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u32 code_entry_point;
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/** 256B aligned Physical sysmem/FB Address where data is located. */
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struct falc_u64 data_dma_base;
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u32 data_size;
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/** Size of data block. Should be multiple of 256B. */
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u32 data_size;
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/** Arguments to be passed to the target firmware being loaded. */
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u32 argc;
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/**
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* Number of arguments to be passed to the target firmware
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* being loaded.
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*/
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u32 argv;
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};
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/* ACR HS ucode interface */
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/**
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* ACR HS ucode load & bootstrap interfaces:
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* ACR HS ucode is read from the filesystem based on the chip-id by the ACR
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* unit. Read ACR HS ucode will be update with below structs by patching at
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* offset present in struct #struct acr_fw_header member hdr_offset. Read
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* ACR HS ucode is loaded onto PMU/SEC2/GSP engines Falcon to bootstrap
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* ACR HS ucode. ACR HS ucode does self-authentication using H/W based
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* HS authentication methodology. Once authenticated the ACR HS ucode
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* starts executing on the falcon.
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*/
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/*
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/**
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* Supporting maximum of 2 regions.
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* This is needed to pre-allocate space in DMEM
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*/
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#define NVGPU_FLCN_ACR_MAX_REGIONS (2U)
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#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200U)
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/*
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* start_addr - Starting address of region
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* end_addr - Ending address of region
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* region_id - Region ID
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* read_mask - Read Mask
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* write_mask - WriteMask
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* client_mask - Bit map of all clients currently using this region
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/**
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* The descriptor used by ACR HS ucode to figure out properties of individual
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* WPR regions.
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*
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* On GV11B, this struct members are set to 0x0 by default, reason
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* to fetch WPR1 details from H/W.
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*/
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struct flcn_acr_region_prop {
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/** Starting address of WPR region */
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u32 start_addr;
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/** Ending address of WPR region */
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u32 end_addr;
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/** The ID of the WPR region. 0 for WPR1 and 1 for WPR2 */
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u32 region_id;
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/** Read mask associated with this region */
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u32 read_mask;
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/** Write mask associated with this region */
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u32 write_mask;
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/** Bit map of all clients currently using this region */
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u32 client_mask;
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/**
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* sysmem/FB location from where contents need to be copied to
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* startAddress
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*/
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u32 shadowmMem_startaddress;
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};
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/*
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* no_regions - Number of regions used.
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* region_props - Region properties
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/**
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* The descriptor used by ACR HS ucode to figure out supporting regions &
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* its properties.
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*/
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struct flcn_acr_regions {
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/** Number of regions used by NVGPU.*/
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u32 no_regions;
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/** Region properties */
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struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
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};
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/*
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* reserved_dmem-When the bootstrap owner has done bootstrapping other falcons,
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* and need to switch into LS mode, it needs to have its own
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* actual DMEM image copied into DMEM as part of LS setup. If
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* ACR desc is at location 0, it will definitely get overwritten
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* causing data corruption. Hence we are reserving 0x200 bytes
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* to give room for any loading data. NOTE: This has to be the
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* first member always
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* signature - Signature of ACR ucode.
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* wpr_region_id - Region ID holding the WPR header and its details
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* wpr_offset - Offset from the WPR region holding the wpr header
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* regions - Region descriptors
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* nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
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* nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob
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/**
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* The descriptor used by ACR HS ucode to figure out the
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* WPR & non-WPR blob details.
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*/
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struct flcn_acr_desc {
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/*
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* The bootstrap owner needs to switch into LS mode when bootstrapping
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* other LS Falcons is completed. It needs to have its own actual
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* DMEM image copied into DMEM as part of LS setup. If ACR desc is
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* at location 0, it will definitely get overwritten causing data
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* corruption. Hence need to reserve 0x200 bytes to give room for
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* any loading data.
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* NOTE: This has to be the first member always.
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*/
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union {
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u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
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} ucode_reserved_space;
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/** Signature of ACR ucode. */
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u32 signatures[4];
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/*Always 1st*/
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/**
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* WPR Region ID holding the WPR header and its details
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*
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* on GV11B, wpr_region_id set to 0x0 by default to indicate
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* to ACR HS ucode to fetch WPR region details from H/W &
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* updating WPR start_addr, end_addr, read_mask & write_mask
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* of struct #flcn_acr_region_prop.
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*/
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u32 wpr_region_id;
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/** Offset from the non-WPR base holding the wpr header */
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u32 wpr_offset;
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/** usable memory ranges, on GV11B it is not set */
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u32 mmu_mem_range;
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/**
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* WPR Region descriptors to provide info about WPR.
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* on GV11B, no_regions set to 1 & region properties value to 0x0
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* to indicate to ACR HS ucode to fetch WPR region details from H/W.
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*/
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struct flcn_acr_regions regions;
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/** stores the size of the ucode blob. */
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u32 nonwpr_ucode_blob_size;
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/**
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* stores sysmem/FB's non-WPR start address where kernel stores
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* ucode blob
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*/
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u64 nonwpr_ucode_blob_start;
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u32 dummy[4]; /* ACR_BSI_VPR_DESC */
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/** dummy space, not used by iGPU */
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u32 dummy[4];
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};
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#endif /* NVGPU_ACR_INTERFACE_H */
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