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gpu: nvgpu: disable ssync access when MIG is enabled

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Disable access to ssync unit when MIG is enabled as ssync is
part of GR and not Compute. A runtime check is now added for the below
function.

gv11b_gr_intr_enable_hww_exceptions

The following priv errors are seen.

SYS write error: ADR 0x00405a14 WRDAT 0xc0000000 master 0x00000000
[ERR]  INFO 0x19400200: (subid 0x00000019 priv_level 0 local_ordering 1)
[ERR]  CODE 0xbadf1100

Jira NVGPU-6699

Change-Id: I9a08f1b6ab58affdcaa18e8ca314a4a00478a3e5
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2514761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Debarshi Dutta
2021-04-14 14:40:26 +05:30
committed by mobile promotions
parent 643eb158a3
commit e9a8fa028e
1 changed files with 5 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
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@@ -779,9 +779,11 @@ void gv11b_gr_intr_enable_hww_exceptions(struct gk20a *g)
nvgpu_writel(g, gr_ds_hww_esr_r(), nvgpu_writel(g, gr_ds_hww_esr_r(),
gr_ds_hww_esr_en_enabled_f() | gr_ds_hww_esr_en_enabled_f() |
gr_ds_hww_esr_reset_task_f()); gr_ds_hww_esr_reset_task_f());
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
nvgpu_writel(g, gr_ssync_hww_esr_r(), nvgpu_writel(g, gr_ssync_hww_esr_r(),
gr_ssync_hww_esr_en_enable_f() | gr_ssync_hww_esr_en_enable_f() |
gr_ssync_hww_esr_reset_active_f()); gr_ssync_hww_esr_reset_active_f());
}
nvgpu_writel(g, gr_mme_hww_esr_r(), nvgpu_writel(g, gr_mme_hww_esr_r(),
gr_mme_hww_esr_en_enable_f() | gr_mme_hww_esr_en_enable_f() |
gr_mme_hww_esr_reset_active_f()); gr_mme_hww_esr_reset_active_f());