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gpu: nvgpu: move init_engine_info from fifo to engine

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Move init_engine_info from fifo to engine unit

Rename init_engine_info to init_info

Rename gm20b_fifo_init_engine_info to nvgpu_engine_init_info

JIRA NVGPU-1313

Change-Id: I30186a601ed004a125018ac1ccda0284273b83c4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085408
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-29 15:50:18 -07:00
committed by mobile promotions
parent d0f45117f1
commit ea1649ab6b
12 changed files with 77 additions and 74 deletions
Download Patch File Download Diff File Expand all files Collapse all files

69
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -34,6 +34,7 @@
#include <nvgpu/power_features/pg.h>
#include <nvgpu/channel.h>
#include <nvgpu/soc.h>
#include <nvgpu/top.h>
#include "gk20a/fifo_gk20a.h"
@@ -51,7 +52,7 @@ enum nvgpu_fifo_engine nvgpu_engine_enum_from_type(struct gk20a *g,
* runlist at this point. We can identify the
* NVGPU_ENGINE_GRCE_GK20A type CE using runlist_id
* comparsion logic with GR runlist_id in
* init_engine_info()
* init_info()
*/
ret = NVGPU_ENGINE_ASYNC_CE_GK20A;
} else {
@@ -471,7 +472,7 @@ int nvgpu_engine_setup_sw(struct gk20a *g)
}
(void) memset(f->active_engines_list, 0xff, size);
err = g->ops.fifo.init_engine_info(f);
err = g->ops.engine.init_info(f);
if (err != 0) {
nvgpu_err(g, "init engine info failed");
goto clean_up;
@@ -732,3 +733,67 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg)
return engines;
}
int nvgpu_engine_init_info(struct fifo_gk20a *f)
{
struct gk20a *g = f->g;
int ret = 0;
enum nvgpu_fifo_engine engine_enum;
u32 pbdma_id = U32_MAX;
bool found_pbdma_for_runlist = false;
f->num_engines = 0;
if (g->ops.top.get_device_info != NULL) {
struct nvgpu_device_info dev_info;
struct fifo_engine_info_gk20a *info;
ret = g->ops.top.get_device_info(g, &dev_info,
NVGPU_ENGINE_GRAPHICS, 0);
if (ret != 0) {
nvgpu_err(g,
"Failed to parse dev_info table for engine %d",
NVGPU_ENGINE_GRAPHICS);
return -EINVAL;
}
found_pbdma_for_runlist = g->ops.fifo.find_pbdma_for_runlist(f,
dev_info.runlist_id,
&pbdma_id);
if (!found_pbdma_for_runlist) {
nvgpu_err(g, "busted pbdma map");
return -EINVAL;
}
engine_enum = nvgpu_engine_enum_from_type(g,
dev_info.engine_type);
info = &g->fifo.engine_info[dev_info.engine_id];
info->intr_mask |= BIT32(dev_info.intr_id);
info->reset_mask |= BIT32(dev_info.reset_id);
info->runlist_id = dev_info.runlist_id;
info->pbdma_id = pbdma_id;
info->inst_id = dev_info.inst_id;
info->pri_base = dev_info.pri_base;
info->engine_enum = engine_enum;
info->fault_id = dev_info.fault_id;
/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
f->active_engines_list[f->num_engines] = dev_info.engine_id;
++f->num_engines;
nvgpu_log_info(g,
"gr info: engine_id %d runlist_id %d intr_id %d "
"reset_id %d engine_type %d engine_enum %d inst_id %d",
dev_info.engine_id,
dev_info.runlist_id,
dev_info.intr_id,
dev_info.reset_id,
dev_info.engine_type,
engine_enum,
dev_info.inst_id);
}
ret = g->ops.fifo.init_ce_engine_info(f);
return ret;
}

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -428,7 +428,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.tsg_open = vgpu_tsg_open,
.tsg_release = vgpu_tsg_release,
.force_reset_ch = vgpu_fifo_force_reset_ch,
.init_engine_info = vgpu_fifo_init_engine_info,
.dump_channel_status_ramfc = NULL,
.is_preempt_pending = NULL,
.reset_enable_hw = NULL,
@@ -461,6 +460,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.engine = {
.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,
.get_mask_on_id = NULL,
.init_info = vgpu_fifo_init_engine_info,
},
.pbdma = {
.intr_enable = NULL,

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -509,7 +509,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.tsg_open = vgpu_tsg_open,
.tsg_release = vgpu_tsg_release,
.force_reset_ch = vgpu_fifo_force_reset_ch,
.init_engine_info = vgpu_fifo_init_engine_info,
.dump_channel_status_ramfc = NULL,
.is_preempt_pending = gv11b_fifo_is_preempt_pending,
.reset_enable_hw = NULL,
@@ -547,6 +546,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.engine = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.get_mask_on_id = NULL,
.init_info = vgpu_fifo_init_engine_info,
},
.pbdma = {
.intr_enable = NULL,

63
drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
View File

@@ -63,69 +63,6 @@ void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch)
}
}
int gm20b_fifo_init_engine_info(struct fifo_gk20a *f)
{
struct gk20a *g = f->g;
int ret = 0;
enum nvgpu_fifo_engine engine_enum;
u32 pbdma_id = U32_MAX;
bool found_pbdma_for_runlist = false;
f->num_engines = 0;
if (g->ops.top.get_device_info != NULL) {
struct nvgpu_device_info dev_info;
struct fifo_engine_info_gk20a *info;
ret = g->ops.top.get_device_info(g, &dev_info,
NVGPU_ENGINE_GRAPHICS, 0);
if (ret != 0) {
nvgpu_err(g,
"Failed to parse dev_info table for engine %d",
NVGPU_ENGINE_GRAPHICS);
return -EINVAL;
}
found_pbdma_for_runlist = g->ops.fifo.find_pbdma_for_runlist(f,
dev_info.runlist_id,
&pbdma_id);
if (!found_pbdma_for_runlist) {
nvgpu_err(g, "busted pbdma map");
return -EINVAL;
}
engine_enum = nvgpu_engine_enum_from_type(g,
dev_info.engine_type);
info = &g->fifo.engine_info[dev_info.engine_id];
info->intr_mask |= BIT32(dev_info.intr_id);
info->reset_mask |= BIT32(dev_info.reset_id);
info->runlist_id = dev_info.runlist_id;
info->pbdma_id = pbdma_id;
info->inst_id = dev_info.inst_id;
info->pri_base = dev_info.pri_base;
info->engine_enum = engine_enum;
info->fault_id = dev_info.fault_id;
/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
f->active_engines_list[f->num_engines] = dev_info.engine_id;
++f->num_engines;
nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d intr_id %d "
"reset_id %d engine_type %d engine_enum %d inst_id %d",
dev_info.engine_id,
dev_info.runlist_id,
dev_info.intr_id,
dev_info.reset_id,
dev_info.engine_type,
engine_enum,
dev_info.inst_id);
}
ret = g->ops.fifo.init_ce_engine_info(f);
return 0;
}
int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
{
struct gk20a *g = f->g;

1
drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
View File

@@ -31,7 +31,6 @@ struct mmu_fault_info;
void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch);
int gm20b_fifo_init_engine_info(struct fifo_gk20a *f);
int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f);
#endif /* NVGPU_GM20B_FIFO_GM20B_H */

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -614,7 +614,6 @@ static const struct gpu_ops gm20b_ops = {
.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
.force_reset_ch = gk20a_fifo_force_reset_ch,
.init_pbdma_info = gk20a_fifo_init_pbdma_info,
.init_engine_info = gm20b_fifo_init_engine_info,
.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
.is_preempt_pending = gk20a_fifo_is_preempt_pending,
.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
@@ -651,6 +650,7 @@ static const struct gpu_ops gm20b_ops = {
.engine = {
.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
},
.pbdma = {
.intr_enable = gm20b_pbdma_intr_enable,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -702,7 +702,6 @@ static const struct gpu_ops gp10b_ops = {
.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
.force_reset_ch = gk20a_fifo_force_reset_ch,
.init_pbdma_info = gk20a_fifo_init_pbdma_info,
.init_engine_info = gm20b_fifo_init_engine_info,
.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
.is_preempt_pending = gk20a_fifo_is_preempt_pending,
.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
@@ -739,6 +738,7 @@ static const struct gpu_ops gp10b_ops = {
.engine = {
.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
},
.pbdma = {
.intr_enable = gm20b_pbdma_intr_enable,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -878,7 +878,6 @@ static const struct gpu_ops gv100_ops = {
.tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted,
.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
.force_reset_ch = gk20a_fifo_force_reset_ch,
.init_engine_info = gm20b_fifo_init_engine_info,
.init_pbdma_info = gk20a_fifo_init_pbdma_info,
.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
.is_preempt_pending = gv11b_fifo_is_preempt_pending,
@@ -922,6 +921,7 @@ static const struct gpu_ops gv100_ops = {
.engine = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -833,7 +833,6 @@ static const struct gpu_ops gv11b_ops = {
.tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted,
.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
.force_reset_ch = gk20a_fifo_force_reset_ch,
.init_engine_info = gm20b_fifo_init_engine_info,
.init_pbdma_info = gk20a_fifo_init_pbdma_info,
.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
.is_preempt_pending = gv11b_fifo_is_preempt_pending,
@@ -877,6 +876,7 @@ static const struct gpu_ops gv11b_ops = {
.engine = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,

2
drivers/gpu/nvgpu/include/nvgpu/engines.h
View File

@@ -27,6 +27,7 @@
struct gk20a;
struct fifo_engine_info_gk20a;
struct fifo_gk20a;
enum nvgpu_fifo_engine {
NVGPU_ENGINE_GR_GK20A = 0U,
@@ -72,5 +73,6 @@ u32 nvgpu_engine_id_to_mmu_fault_id(struct gk20a *g, u32 engine_id);
u32 nvgpu_engine_mmu_fault_id_to_engine_id(struct gk20a *g, u32 fault_id);
u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg);
int nvgpu_engine_init_info(struct fifo_gk20a *f);
#endif /*NVGPU_ENGINE_H*/

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -949,7 +949,6 @@ struct gpu_ops {
int (*tsg_open)(struct tsg_gk20a *tsg);
void (*tsg_release)(struct tsg_gk20a *tsg);
int (*init_pbdma_info)(struct fifo_gk20a *f);
int (*init_engine_info)(struct fifo_gk20a *f);
void (*free_channel_ctx_header)(struct channel_gk20a *ch);
void (*dump_channel_status_ramfc)(struct gk20a *g,
struct gk20a_debug_output *o,
@@ -1069,6 +1068,7 @@ struct gpu_ops {
u32 engine_subid);
u32 (*get_mask_on_id)(struct gk20a *g,
u32 id, bool is_tsg);
int (*init_info)(struct fifo_gk20a *f);
} engine;
struct {

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -913,7 +913,6 @@ static const struct gpu_ops tu104_ops = {
.tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted,
.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
.force_reset_ch = gk20a_fifo_force_reset_ch,
.init_engine_info = gm20b_fifo_init_engine_info,
.init_pbdma_info = gk20a_fifo_init_pbdma_info,
.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
.is_preempt_pending = gv11b_fifo_is_preempt_pending,
@@ -959,6 +958,7 @@ static const struct gpu_ops tu104_ops = {
.engine = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,