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video: tegra: host: add gm20b channel op

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Bug 1450792

Change-Id: I09f7c727a773178613fe555eb025ac324da0008e
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/381128
Reviewed-on: http://git-master/r/396373
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
This commit is contained in:
Kevin Huang
2014-03-12 16:35:47 -07:00
committed by Dan Willemsen
parent 9eb1f57ba2
commit ea3d83d98b
4 changed files with 71 additions and 0 deletions
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1
drivers/gpu/nvgpu/gm20b/Makefile
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@@ -8,4 +8,5 @@ obj-$(CONFIG_GK20A) = \
gr_gm20b.o \
gr_gm20b.o \
fb_gm20b.o \
fifo_gm20b.o \
gm20b_gating_reglist.o

47
drivers/gpu/nvgpu/gm20b/fifo_gm20b.c Normal file
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@@ -0,0 +1,47 @@
/*
* GM20B Fifo
*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "gk20a/gk20a.h"
#include "fifo_gm20b.h"
#include "hw_ccsr_gm20b.h"
#include "hw_ram_gm20b.h"
static void channel_gm20b_bind(struct channel_gk20a *ch_gk20a)
{
struct gk20a *g = ch_gk20a->g;
u32 inst_ptr = ch_gk20a->inst_block.cpu_pa
>> ram_in_base_shift_v();
gk20a_dbg_info("bind channel %d inst ptr 0x%08x",
ch_gk20a->hw_chid, inst_ptr);
ch_gk20a->bound = true;
gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid),
ccsr_channel_inst_ptr_f(inst_ptr) |
ccsr_channel_inst_target_vid_mem_f() |
ccsr_channel_inst_bind_true_f());
gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid),
(gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) &
~ccsr_channel_enable_set_f(~0)) |
ccsr_channel_enable_set_true_f());
}
void gm20b_init_fifo(struct gpu_ops *gops)
{
gops->fifo.bind_channel = channel_gm20b_bind;
}

21
drivers/gpu/nvgpu/gm20b/fifo_gm20b.h Normal file
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@@ -0,0 +1,21 @@
/*
* GM20B Fifo
*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _NVHOST_GM20B_FIFO
#define _NVHOST_GM20B_FIFO
struct gk20a;
void gm20b_init_fifo(struct gpu_ops *gops);
#endif

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -22,6 +22,7 @@
#include "ltc_gm20b.h"
#include "fb_gm20b.h"
#include "gm20b_gating_reglist.h"
#include "fifo_gm20b.h"
struct gpu_ops gm20b_ops = {
.clock_gating = {
@@ -45,6 +46,7 @@ int gm20b_init_hal(struct gpu_ops *gops)
gm20b_init_gr(gops);
gm20b_init_ltc(gops);
gm20b_init_fb(gops);
gm20b_init_fifo(gops);
gops->name = "gm20b";
return 0;